PI7C7300 datasheet(30/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 30 OF 109

09/25/03 Revision 1.09

PI7C7300A has the capability to post multiple delayed read requests, up to a maximum

of four in each direction. If an initiator starts a read transaction that matches the address

and read command of a read transaction that is already queued, the current read

command is not posted as it is already contained in the delayed transaction queue.

See Section 6 for a discussion of how delayed read transactions are ordered when

crossing PI7C7300A.

4.7.7

FAST BACK-TO-BACK READ TRANSACTION

PI7C7300A can recognize fast back-to-back read transactions.

4.8

CONFIGURATION TRANSACTIONS

Configuration transactions are used to initialize a PCI system. Every PCI device

has a configuration space that is accessed by configuration commands. All registers are

accessible in configuration space only.

In addition to accepting configuration transactions for initialization of its own

configuration space, the PI7C7300A also forwards configuration transactions for device

initialization in hierarchical PCI systems, as well as for special cycle generation.

To support hierarchical PCI bus systems, two types of configuration transactions are

specified: Type 0 and Type 1.

Type 0 configuration transactions are issued when the intended target resides on the same

PCI bus as the initiator. A Type 0 configuration transaction is identified by the

configuration command and the lowest two bits of the address set to 00b.

Type 1 configuration transactions are issued when the intended target resides on another

PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1

configuration command is identified by the configuration command and the lowest two

address bits set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the DWORD

address of the configuration register to be accessed. The function number is also included

in both Type 0 and Type 1 formats and indicates which function of a multifunction

device is to be accessed. For single-function devices, this value is not decoded. The

addresses of Type 1 configuration transaction include a 5-bit field designating the device

number that identifies the device on the target PCI bus that is to be accessed. In addition,

the bus number in Type 1 transactions specifies the PCI bus to which the transaction is

targeted.

4.8.1

TYPE 0 ACCESS TO PI7C7300A

The configuration space is accessed by a Type 0 configuration transaction on the primary

interface. The configuration space cannot be accessed from the secondary bus. The

PI7C7300A responds to a Type 0 configuration transaction by asserting P_DEVSEL#

when the following conditions are met during the address phase:

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