PI7C7300 datasheet(23/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 23 OF 109

09/25/03 Revision 1.09

A transfer of data occurs only when both IRDY# and TRDY# are asserted during the

same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is

de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are

asserted. See Section 4.9 for further discussion of transaction termination.

Depending on the command type, PI7C7300A can support multiple data phase

PCI transactions. For detailed descriptions of how PI7C7300A imposes disconnect

boundaries, see Section 4.6.4 for write address boundaries and Section 4.7.3 read address

boundaries.

4.6

WRITE TRANSACTIONS

Write transactions are treated as either posted write or delayed write transactions.

Table 4-2 shows the method of forwarding used for each type of write operation.

Table 4-2 WRITE TRANSACTION FORWARDING

Type of Transaction

Type of Forwarding

Memory Write

Posted (except VGA memory)

Memory Write and Invalidate

Posted

Memory Write to VGA memory

Delayed

I/O Write

Delayed

Type 1 Configuration Write

Delayed

4.6.1

MEMORY WRITE TRANSACTIONS

Posted write forwarding is used for “Memory Write” and “Memory Write and

Invalidate” transactions.

When PI7C7300A determines that a memory write transaction is to be forwarded across

the bridge, PI7C7300A asserts DEVSEL# with medium timing and TRDY# in the next

cycle, provided that enough buffer space is available in the posted memory write queue

for the address and at least one DWORD of data. Under this condition, PI7C7300A

accepts write data without obtaining access to the target bus. The PI7C7300A can accept

one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted.

The write data is stored in an internal posted write buffers and is subsequently delivered

to the target. The PI7C7300A continues to accept write data until one of the following

events occurs:

The initiator terminates the transaction by de-asserting FRAME# and IRDY#.

An internal write address boundary is reached, such as a cache line boundary or an

aligned 4KB boundary, depending on the transaction type.

The posted write data buffer fills up.

When one of the last two events occurs, the PI7C7300A returns a target disconnect to the

requesting initiator on this data phase to terminate the transaction.

Once the posted write data moves to the head of the posted data queue, PI7C7300A

asserts its request on the target bus. This can occur while PI7C7300A is still receiving

data on the initiator bus. When the grant for the target bus is received and the target bus

is detected in the idle condition, PI7C7300A asserts FRAME# and drives the stored write

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