PI7C7300 datasheet(29/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 29 OF 109

09/25/03 Revision 1.09

If PI7C7300A is unable to obtain read data from the target after 224 (default) or 232

(maximum) attempts, PI7C7300A will report a system error. The number of attempts is

programmable. PI7C7300A also asserts P_SERR# if the primary SERR# enable bit is set

in the command register. See Section 7.4 for information on the assertion of P_SERR#.

Once PI7C7300A receives DEVSEL# and TRDY# from the target, it transfers the data

read to the opposite direction read data queue, pointing toward the opposite inter-face,

before terminating the transaction. For example, read data in response to a downstream

read transaction initiated on the primary bus is placed in the upstream read data queue.

The PI7C7300A can accept one DWORD of read data each PCI clock cycle; that is, no

master wait states are inserted. The number of DWORD transferred during a delayed

read transaction depends on the conditions given in Table 4-5 (assuming no disconnect is

received from the target).

4.7.6

DELAYED READ COMPLETION ON INITIATOR BUS

When the transaction has been completed on the target bus, and the delayed read data is

at the head of the read data queue, and all ordering constraints with posted write

transactions have been satisfied, the PI7C7300A transfers the data to the initiator when

the initiator repeats the transaction. For memory read transactions, PI7C7300A aliases

the memory read, memory read line, and memory read multiple bus commands when

matching the bus command of the transaction to the bus command in the delayed

transaction queue. PI7C7300A returns a target disconnect along with the transfer of the

last DWORD of read data to the initiator. If PI7C7300A initiator terminates the

transaction before all read data has been transferred, the remaining read data left in data

buffers is discarded.

When the master repeats the transaction and starts transferring prefetchable read data

from data buffers while the read transaction on the target bus is still in progress and

before a read boundary is reached on the target bus, the read transaction starts operating

in flow-through mode. Because data is flowing through the data buffers from the target to

the initiator, long read bursts can then be sustained. In this case, the read transaction is

allowed to continue until the initiator terminates the trans-action, or until an aligned 4KB

address boundary is reached, or until the buffer fills, whichever comes first. When the

buffer empties, PI7C7300A reflects the stalled condition to the initiator by disconnecting

the initiator with data. The initiator may retry the transaction later if data are needed. If

the initiator does not need any more data, the initiator will not continue the disconnected

transaction. In this case, PI7C7300A will start the master timeout timer. The remaining

read data will be discarded after the master timeout timer expires. To provide better

latency, if there are any other pending data for other transactions in the RDB (Read Data

Buffer), the remaining read data will be discarded even though the master timeout timer

has not expired.

PI7C7300A implements a master timeout timer that starts counting when the delayed

read completion is at the head of the delayed transaction queue, and the read data is at the

head of the read data queue. The initial value of this timer is program-mable through

configuration register. If the initiator does not repeat the read transaction and before the

master timeout timer expires (215 default), PI7C7300A discards the read transaction and

read data from its queues. PI7C7300A also conditionally asserts P_SERR# (see Section

7.4).

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