PI7C7300 datasheet(52/109 Pages) PERICOM

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PI7C7300A

3-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 52 OF 109

09/25/03 Revision 1.09

PI7C7300A sets the data parity detected bit in the secondary status register, if the

secondary interface parity error response bit is set in the bridge control register.

PI7C7300A forwards the bad parity with the data back to the initiator on the primary

bus. If the data with the bad parity is pre-fetched and is not read by the initiator on

the primary bus, the data is discarded and the data with bad parity is not returned to

the initiator.

PI7C7300A completes the transaction normally.

For upstream transactions, when PI7C7300A detects a read data parity error on the

primary bus, the following events occur:

PI7C7300A asserts P_PERR# two cycles following the data transfer, if the primary

interface parity error response bit is set in the command register.

PI7C7300A sets the detected parity error bit in the primary status register.

PI7C7300A sets the data parity detected bit in the primary status register, if the

primary interface parity-error-response bit is set in the command register.

PI7C7300A forwards the bad parity with the data back to the initiator on the

secondary bus. If the data with the bad parity is pre-fetched and is not read by the

initiator on the secondary bus, the data is discarded and the data with bad parity is

not returned to the initiator.

PI7C7300A completes the transaction normally.

PI7C7300A returns to the initiator the data and parity that was received from the target.

When the initiator detects a parity error on this read data and is enabled to report it, the

initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the

initiator takes responsibility for handling a parity error condition; therefore, when

PI7C7300A detects PERR# asserted while returning read data to the initiator,

PI7C7300A does not take any further action and completes the transaction normally.

7.2.3

DELAYED WRITE TRANSACTIONS

When PI7C7300A detects a data parity error during a delayed write transaction, the

initiator drives data and data parity, and the target checks parity and conditionally asserts

PERR#.

For delayed write transactions, a parity error can occur at the following times:

During the original delayed write request transaction

When the initiator repeats the delayed write request transaction

When PI7C7300A completes the delayed write transaction to the target

When a delayed write transaction is normally queued, the address, command, address

parity, data, byte enable bits, and data parity are all captured and a target retry is returned

PI7C7300 Datasheet(PDF) 52 Page - Pericom Semiconductor Corporation