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PI7C7300 Datasheet(PDF) 21 Page - Pericom Semiconductor Corporation

Part # PI7C7300
Description  3-PORT PCI-to-PCI BRIDGE
PDF  109 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI7C7300 Datasheet(HTML) 21 Page - Pericom Semiconductor Corporation

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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 21 OF 109
09/25/03 Revision 1.09
Pin #
Name
Type
Pin #
Name
Type
Y17
P_AD[11]
PB
Y18
P_AD[8]
PB
Y19
P_AD[5]
PB
Y20
P_AD[2]
PB
4
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C7300A, and transaction termination. The PI7C7300A has three 128-byte buffers for
buffering of upstream and downstream transactions.
These hold addresses, data,
commands, and byte enables and are used for both read and write transactions.
4.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C7300A.
Table 4-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C7300A initiates
transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when
PI7C7300A responds to transactions as a target, on the primary (P) and secondary (S1,
S2) buses.
Table 4-1 PCI TRANSACTIONS
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000
Interrupt Acknowledge
N
N
N
N
0001
Special Cycle
Y
Y
N
N
0010
I/O Read
Y
Y
Y
Y
0011
I/O Write
Y
Y
Y
Y
0100
Reserved
N
N
N
N
0101
Reserved
N
N
N
N
0110
Memory Read
Y
Y
Y
Y
0111
Memory Write
Y
Y
Y
Y
1000
Reserved
N
N
N
N
1001
Reserved
N
N
N
N
1010
Configuration Read
N
Y
Y
N
1011
Configuration Write
Y (Type 1 only)
Y
Y
Y (Type 1 only)
1100
Memory Read Multiple
Y
Y
Y
Y
1101
Dual Address Cycle
Y
Y
Y
Y
1110
Memory Read Line
Y
Y
Y
Y
1111
Memory Write and Invalidate
Y
Y
Y
Y
As indicated in Table 4-1, the following PCI commands are not supported by
PI7C7300A:
!
PI7C7300A never initiates a PCI transaction with a reserved command code and, as
a target, PI7C7300A ignores reserved command codes.
!
PI7C7300A does not generate interrupt acknowledge transactions. PI7C7300A
ignores interrupt acknowledge transactions as a target.
!
PI7C7300A does not respond to special cycle transactions. PI7C7300A cannot
guarantee delivery of a special cycle transaction to downstream buses because of the



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