DM505 datasheet(152/290 Pages) TI1

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sclk

d[0]

d[3:1]

Bit n-1

Bit n-2

Bit 1

Bit 0

PHA=1

POL=1

Command

Write Data

SPRS85v_TIMING_OSPI1_03

152

DM505

SPRS976D – NOVEMBER 2016 – REVISED JULY 2017

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Specifications

Table 5-50. Timing Requirements for QSPI

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tsu(D-RTCLK)

Setup time, d[3:0] valid before falling rtclk edge

Default

Timing

Mode,

Clock

Mode 0

2.9

tsu(D-SCLK)

Setup time, d[3:0] valid before falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

5.7

th(RTCLK-D)

Hold time, d[3:0] valid after falling rtclk edge

Default

Timing

Mode,

Clock

Mode 0

-0.1

th(SCLK-D)

Hold time, d[3:0] valid after falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

0.1

tsu(D-SCLK)

Setup time, final d[3:0] bit valid before final falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

5.7-P (1)

th(SCLK-D)

Hold time, final d[3:0] bit valid after final falling sclk edge

Default

Timing

Mode,

Clock

Mode 3

0.1+P (1)

(1) P = SCLK period.

(2) Clock Modes 1 and 2 are not supported.

(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although

non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Modes 0 and 3.

Figure 5-41. QSPI Write (Clock Mode 3)

DM505 Datasheet(PDF) 152 Page - Texas Instruments

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