DM505 datasheet(156/290 Pages) TI1

156 / 290 page

156

DM505

SPRS976D – NOVEMBER 2016 – REVISED JULY 2017

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Specifications

Table 5-54. Timing Requirements for McASP3 (1) (continued)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

th(ACLK-AFSRX)

Hold time, AFSR/X input valid after ACLKR/X

ACLKR/X int

0.5

ACLKR/X ext in

ACLKR/X ext out

0.4

tsu(AXR-ACLK)

Setup time, AXR input valid before ACLKX

ACLKX int (ASYNC=0)

18.2

ACLKR/X ext in

ACLKR/X ext out

th(ACLK-AXR)

Hold time, AXR input valid after ACLKX

ACLKX int (ASYNC=0)

0.5

ACLKR/X ext in

ACLKR/X ext out

0.5

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2) P = AHCLKX period in ns.

(3) R = ACLKR/X period in ns.

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