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AD9681 Datasheet(PDF) 15 Page - Analog Devices

Part # AD9681
Description  1.8 V Analog-to-Digital Converter
PDF  41 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9681 Datasheet(HTML) 15 Page - Analog Devices

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AD9681
Data Sheet
Rev. C | Page 14 of 40
Pin No.
Mnemonic
Description
J12, J11
D0−A2,
D0+A2
Channel A Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output
True (Default Two-Lane Mode) or Disabled (One-Lane Mode).
K12, K11
D1−A2,
D1+A2
Channel A Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output
True (Default Two-Lane Mode) or Disabled (One-Lane Mode).
L12, L11
D0−B1,
D0+B1
Channel B Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output
True (Default Two-Lane Mode) or Channel A Bank 1 Digital Output Complement,
Digital Output True (One-Lane Mode).
M12, M11
D1−B1,
D1+B1
Channel B Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output
True (Default Two-Lane Mode) or Channel B Bank 1 Digital Output Complement,
Digital Output True (One-Lane Mode).
M10, L10
D0−B2,
D0+B2
Channel B Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output
True (Default Two-Lane Mode). Channel A Bank 2 Digital Output Complement,
Digital Output True (One-Lane Mode).
M9, L9
D1−B2,
D1+B2
Channel B Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output
True (Default Two-Lane Mode) or Channel B Bank 2 Digital Output Complement,
Digital Output True (One-Lane Mode).
M4, L4
D0−C1,
D0+C1
Channel C Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output
True (Default Two-Lane Mode) or Channel C Bank 1 Digital Output Complement,
Digital Output True (One-Lane Mode).
M3, L3
D1−C1,
D1+C1
Channel C Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output
True (Default Two-Lane Mode) or Channel D Bank 1 Digital Output Complement,
Digital Output True (One-Lane Mode).
M1, M2
D0−C2,
D0+C2
Channel C Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output
True (Default Two-Lane Mode) or Channel C Bank 2 Digital Output Complement,
Digital Output True (One-Lane Mode).
L1, L2
D1−C2,
D1+C2
Channel C Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output
True (Default Two-Lane Mode) or Channel D Bank 2 Digital Output Complement,
Digital Output True (One-Lane Mode).
K1, K2
D0−D1,
D0+D1
Channel D Lane 0 Bank 1 Digital Output Complement, Lane 0 Bank 1 Digital Output
True (Default Two-Lane Mode) or Disabled (One-Lane Mode).
J1, J2
D1−D1,
D1+D1
Channel D Lane 1 Bank 1 Digital Output Complement, Lane 1 Bank 1 Digital Output
True (Default Two-Lane Mode) or Disabled (One-Lane Mode).
H1, H2
D0−D2,
D0+D2
Channel D Lane 0 Bank 2 Digital Output Complement, Lane 0 Bank 2 Digital Output
True (Default Two-Lane Mode) or Disabled (One-Lane Mode).
G1, G2
D1−D2,
D1+D2
Channel D Lane 1 Bank 2 Digital Output Complement, Lane 1 Bank 2 Digital Output
True (Default Two-Lane Mode) or Disabled (One-Lane Mode).
M6, L6;
M7, L7
DCO−1,
DCO+1;
DCO−2,
DCO+2
Data Clock Digital Output Complement, Data Clock Digital Output True. DCO±1 is
used to capture D0±x1/D1±x1 digital output data, and DCO±2 is used to capture
D0±x2/D1±x2 digital output data.
M5, L5;
M8, L8
FCO−1,
FCO+1;
FCO−2,
FCO+2
Frame Clock Digital Output Complement, Frame Clock Digital Output True. FCO±1
frames D0±x1/D1±x1 digital output data, and FCO±2 frames D0±x2/D1±x2 digital
output data.
F12
SCLK/DTP
Serial Clock/Digital Test Pattern.
F11
SDIO/OLM
Serial Data Input/Output/Output Lane Mode.
E10, F10
CSB1, CSB2
Chip Select Bar. CSB1 enables/disables the SPI for four channels in Bank 1; CSB2
enables/ disables the SPI for four channels in Bank 2.
G10
PDWN
Power-Down.
E12, E11
VIN−A1,
VIN+A1
Analog Input Complement, Analog Input True.
C12, C11
VIN−A2,
VIN+A2
Analog Input Complement, Analog Input True.
A12, A11
VIN−B1,
VIN+B1
Analog Input Complement, Analog Input True.
A9, B9
VIN−B2,
VIN+B2
Analog Input Complement, Analog Input True.
A6, B6
VIN−C1,
VIN+C1
Analog Input Complement, Analog Input True.



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