AD9681 datasheet(28/41 Pages) AD

28 / 41 page

Data Sheet

AD9681

Rev. C | Page 27 of 40

Data from each ADC is serialized and provided on a separate

channel in two lanes in DDR mode, which is the default condition.

In the default condition, the data rate for each serial stream is

equal to 8 bits times the sample clock rate, with a maximum of

1 Gbps/lane ((8 bits × 125 MSPS) = 1 Gbps/lane). If one-lane

mode is used, the bit rate doubles. To keep within the 1 Gbps

limit, the maximum allowable sample rate is 62.5 MSPS in one-

lane mode. The lowest typical conversion rate is 10 MSPS. For

conversion rates of less than 20 MSPS, the SPI must be used to

reconfigure the integrated PLL. See Register 0x21 in the

Memory Map section for details on enabling this feature

Two output clock types are provided to assist in capturing data

from the AD9681. DCO±1 and DCO±2 are used to clock the

output data and their frequency is equal to 4× the sample clock

(CLK±) rate for the default mode of operation. Data is clocked out

of the AD9681 and must be captured on the rising and falling edges

of the DCO that supports double data rate (DDR) capturing.

DCO±1 is used to capture the D0±x1/D1±x1 (Bank 1) data;

DCO±2 is used to capture the D0±x2/D1±x2 (Bank 2) data.

FCO±1 and FCO±2 signal the start of a new output byte and

toggle at a rate equal to the sample clock rate in 1× frame mode.

FCO±1 frames the D0±x1/D1±x1 (Bank 1) data and FCO±2

frames the D0±x2/ D1±x2 (Bank 2) data. See the Timing

Diagrams section for more information.

When the SPI is used, the DCO phase can be adjusted in 60°

increments relative to one data cycle (30° relative to one DCO

cycle). This enables the user to refine system timing margins if

required. The default DCO±1 and DCO±2 to output data edge

timing, as shown in Figure 3, is 180° relative to one data cycle

(90° relative to one DCO cycle).

A 12-bit serial stream can also be initiated from the SPI. This

allows the user to implement and test compatibility to lower

resolution systems. When changing the resolution to a 12-bit

serial stream, the data stream is shortened. See Figure 4 for the

12-bit example. However, in the default option with the serial

output number of bits at 16, the data stream stuffs two 0s at the

end of the 14-bit serial data.

In default mode, as shown in Figure 3, the MSB is first in the

data output serial stream. This can be inverted so that the LSB is

first in the data output serial stream by using the SPI.

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing (see Table 11 for the output

bit sequencing options that are available). Some test patterns

have two serial sequential words and can alternate in various

ways, depending on the test pattern chosen. Note that some

patterns do not adhere to the data format select option. In

addition, custom user defined test patterns can be assigned in

Table 11. Flexible Output Test Modes

Output Test Mode Bit

Sequence (Reg. 0x0D)

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to Data

Format Select

Notes

0000

Off (default)

Not applicable

0001

Midscale short

1000 0000 0000 (12-bit)

1000 0000 0000 0000 (16-bit)

Not applicable

Yes

Offset binary

code shown

0010

+Full-scale short

1111 1111 1111 (12-bit)

1111 1111 1111 1100 (16-bit)

Not applicable

Yes

Offset binary

code shown

0011

−Full-scale short

0000 0000 0000 (12-bit)

0000 0000 0000 0000 (16-bit)

Not applicable

Yes

Offset binary

code shown

0100

Checkerboard

1010 1010 1010 (12-bit)

1010 1010 1010 1000 (16-bit)

0101 0101 0101 (12-bit)

0101 0101 0101 0100 (16-bit)

0101

PN sequence long1

Not applicable

Yes

PN23

ITU 0.150

X23 + X18 + 1

0110

PN sequence short1

Not applicable

Yes

PN9

ITU 0.150

X9 + X5 + 1

0111

One-/zero-word

toggle

1111 1111 1111 (12-bit)

111 1111 1111 1100 (16-bit)

0000 0000 0000 (12-bit)

0000 0000 0000 0000 (16-bit)

1000

User input

1001

1-/0-bit toggle

1010 1010 1010 (12-bit)

1010 1010 1010 1000 (16-bit)

Not applicable

1010

1× sync

0000 0011 1111 (12-bit)

0000 0001 1111 1100 (16-bit)

Not applicable

1011

One bit high

1000 0000 0000 (12-bit)

1000 0000 0000 0000 (16-bit)

Not applicable

Pattern

associated with

the external pin

1100

Mixed bit frequency

1010 0011 0011 (12-bit)

1010 0001 1001 1100 (16-bit)

Not applicable

1 All test mode options except PN sequence short and PN sequence long can support 12-bit to 16-bit word lengths to verify data capture to the receiver.

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