AD9681 datasheet(24/41 Pages) AD

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Data Sheet

AD9681

Rev. C | Page 23 of 40

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 44. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516-4/AD9517-4 clock drivers,

noted by AD951x in Figure 44, offer excellent jitter performance.

100Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

Figure 44. Differential PECL Sample Clock (Up to 1 GHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 45. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-4/

AD9517-4 clock drivers, noted by AD951x in Figure 45 and

Figure 46, offer excellent jitter performance.

100Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

Figure 45. Differential LVDS Sample Clock (Up to 1 GHz)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 μF capacitor (see

Figure 46).

OPTIONAL

100Ω

0.1µF

50Ω1

150Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

Figure 46. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9681 contains an input clock divider with the ability

to divide the input clock by integer values from 1 to 8.

The AD9681 clock divider can be synchronized using the external

SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows the clock dividers of multiple devices to

be aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety

of internal timing signals and, as a result, may be sensitive to

clock duty cycle. Commonly, a ±5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9681 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide

a wide range of clock input duty cycles without affecting the per-

formance of the AD9681. Noise and distortion performance are

nearly flat for a wide range of duty cycles with the DCS turned on.

Jitter on the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty cycle

control loop does not function for clock rates of less than 20 MHz,

nominally. The loop has a time constant associated with it that

must be considered in applications in which the clock rate can

change dynamically. A wait time of 1.5 μs to 5 μs is required after

a dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input signal.

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