AD9681 datasheet(29/41 Pages) AD

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AD9681

Data Sheet

Rev. C | Page 28 of 40

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 29 − 1 or 511 bits. Refer to

Section 5.1 of the ITU-T 0.150 (05/96) standard for a descrip-

tion of the PN sequence and how it is generated. The seed value

is all 1s (see Table 12 for the initial values). The output is a parallel

representation of the serial PN9 sequence in MSB-first format.

The first output word is the first 14 bits of the PN9 sequence in

MSB aligned form.

Table 12. PN Sequence

Sequence

Initial

Value

Next Three Output Samples

(MSB First) Twos Complement

PN Sequence Short

0x7F80

0x77C4, 0xF320, 0xA538

PN Sequence Long

0x7FFC

0x7F80, 0x8004, 0x7000

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 or 8,388,607 bits. Refer

to Section 5.6 of the ITU-T 0.150 (05/96) standard for a description

of the PN sequence and how it is generated. The seed value is all 1s

(see Table 12 for the initial values), and the AD9681 inverts the

bit stream with relation to the ITU standard. The output is a

parallel representation of the serial PN23 sequence in MSB-first

format. The first output word is the first 14 bits of the PN23

sequence in MSB aligned format.

Consult the Memory Map section for information on how to

change these additional digital output timing features through

the SPI.

SDIO/OLM Pin

For applications that do not require SPI mode operation, the CSB1

and CSB2 pins are tied to AVDD, and the SDIO/OLM pin controls

the output lane mode according to Table 13.

For applications where the SDIO/OLM pin is not used, tie CSB1

and CSB2 to AVDD. When using the one-lane mode, use an

encode rate of ≤62.5 MSPS to meet the maximum output rate of

1 Gbps.

Table 13. Output Lane Mode Pin Settings

Output Lane

Mode Voltage

(SDIO/OLM Pin)

Output Mode

AVDD (Default)

Two-lane. 1× frame, 16-bit serial output.

GND

One-lane. 1× frame, 16-bit serial output.

SCLK/DTP Pin

The SCLK/DTP pin can enable a single digital test pattern if

it and the CSB1 and CSB2 pins are held high during device

power-up. When SCLK/DTP is tied to AVDD, the ADC channel

outputs shift out the following pattern: 1000 0000 0000 0000.

The FCO±1, FCO±2, DCO±1, and DCO±2 pins function

normally while all channels shift out the repeatable test pattern.

This pattern allows the user to perform timing alignment

adjustments among the FCO±1, FCO±2, DCO±1, DCO±2, and

output data. The SCLK/DTP pin has an internal 30 kΩ resistor

to GND and can be left unconnected for normal operation.

Table 14. Digital Test Pattern Pin Settings

Selected Digital

Test Pattern

DTP Voltage

Resulting

D0±xx and D1±xx

Normal Operation

No connect

Normal operation

DTP

AVDD

1000 0000 0000 0000

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map

section for information about the options available.

CSB1 and CSB2 Pins

Tie the CSB1 and CSB2 pins to AVDD for applications that do

not require SPI mode operation. Tying CSB1 and CSB2 high

causes all SCLK and SDIO SPI communication information to

be ignored.

CSB1 selects/deselects SPI circuitry affecting the D0±x1/D1±x1

outputs (Bank 1). CSB2 selects/deselects SPI circuitry affecting

the D0±x2/D1±x2 (Bank 2) outputs.

It is recommended that CSB1 and CSB2 be controlled with the

same signal; that is, tie them together. In this way, whether tying

them to AVDD or selecting SPI functionality, both banks of

ADCs are controlled identically and are always in the same state.

RBIAS1 and RBIAS2 Pins

To set the internal core bias current of the ADC, place a 10.0 kΩ,

1% tolerance resistor to ground at each of the RBIAS1 and

RBIAS2 pins.

OUTPUT TEST MODES

The AD9681 includes a built-in test feature designed to enable

verification of the integrity of each data output channel, as well

as to facilitate board level debugging. Various output test modes

are provided to place predictable values on the outputs of the

AD9681.

The output test modes are described in Table 11 and controlled by

the output test mode bits at Address 0x0D. When an output test

mode is enabled, the analog section of the ADC is disconnected

from the digital back-end blocks and the test pattern is run through

the output formatting block. Some of the test patterns are subject

to output formatting, and some are not. The PN generators from

the PN sequence tests can be reset by setting Bit 4 or Bit 5 of

analog signal (if present, the analog signal is ignored), but they do

require an encode clock. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

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