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ADT7312

Data Sheet

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SPI TIMING SPECIFICATIONS

TA = −55°C to +175°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns

(10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Table 2.

Parameter1, 2

Limit at TMIN, TMAX

Unit

Description

ns min

CS falling edge to SCLK active edge setup time

100

ns min

SCLK high pulse width

100

ns min

SCLK low pulse width

ns min

Data setup time prior to SCLK rising edge

ns min

Data hold time after SCLK rising edge

ns min

Data access time after SCLK falling edge

ns max

VDD = 4.5 V to 5.5 V

ns max

VDD = 2.7 V to 3.6 V

t73

ns min

Bus relinquish time after CS inactive edge

ns max

ns min

SCLK inactive edge to CS rising edge hold time

ns min

CS falling edge to DOUT active time

ns max

VDD = 4.5 V to 5.5 V

ns max

VDD = 2.7 V to 3.6 V

t10

ns min

SCLK inactive edge to DOUT low

Sample tested during initial release to ensure compliance.

See Figure 2.

The t7 values are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

SCLK

DIN

DOUT

MSB

LSB

MSB

LSB

t10

Figure 2. Detailed SPI Timing Diagram

Rev. A

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