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ADT7312 Datasheet(PDF) 14 Page - Analog Devices

Part # ADT7312
Description  Digital SPI Temperature Sensor in Die Form
PDF  25 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
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ADT7312 Datasheet(HTML) 14 Page - Analog Devices

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Data Sheet
ADT7312
| Page 13 of 24
REGISTERS
The ADT7312 contains eight registers.
•
Status register
•
Configuration register
•
Temperature value register
•
ID register
•
Four temperature setpoint registers
The status register, the temperature value register, and the ID
register are read-only registers.
Table 7. ADT7312 Registers
Register
Address
Register Name
Power-On Default
0x00
Status
0x80
0x01
Configuration
0x00
0x02
Temperature value
0x0000
0x03
ID
0xC3
0x04
TCRIT setpoint
0x4980 (147°C)
0x05
THYST setpoint
0x05 (5°C)
0x06
THIGH setpoint
0x2000 (64°C)
0x07
TLOW setpoint
0x0500 (10°C)
STATUS REGISTER
The 8-bit, read-only status register (Register Address 0x00)
reflects the status of the overtemperature and undertemperature
interrupts that can activate the CT and INT pins. This register
also reflects the status of a temperature conversion operation.
The interrupt flags in the status register (Bits[6:4]) are reset by
a read of the register or when the temperature value returns
within the temperature limits (including hysteresis). The RDY
bit (Bit 7) is reset to 1 after a read of the temperature value
register (Register Address 0x02). In one-shot and 1 SPS modes,
the RDY bit is reset after a write to the operation mode bits of
the configuration register (Register Address 0x01, Bits[6:5]).
Table 8. Status Register (Register Address 0x00)
Bits
Default Value
Type
Name
Description
7
1
R
RDY
This bit is set to 0 when the temperature conversion result is written to the
temperature value register. This bit is reset to 1 when the temperature value register
is read. In one-shot and 1 SPS modes, this bit is reset after a write to the operation
mode bits of the configuration register (Register Address 0x01, Bits[6:5]).
6
0
R
TCRIT
This bit is set to 1 when the temperature exceeds the TCRIT temperature limit. This bit
is cleared to 0 when the status register is read or when the measured temperature
falls below the limit (TCRIT − THYST) set in the TCRIT setpoint and THYST setpoint registers.
5
0
R
THIGH
This bit is set to 1 when the temperature exceeds the THIGH temperature limit. This bit
is cleared to 0 when the status register is read or when the measured temperature
falls below the limit (THIGH − THYST) set in the THIGH setpoint and THYST setpoint registers.
4
0
R
TLOW
This bit is set to 1 when the temperature goes below the TLOW temperature limit. This
bit is cleared to 0 when the status register is read or when the measured temperature
rises above the limit (TLOW + THYST) set in the TLOW setpoint and THYST registers.
[3:0]
0000
R
Unused
Reads back 0000.
Rev. A



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