ADAS1000 datasheet(30/80 Pages) AD

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ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

ELECTRODE/LEAD FORMATION AND INPUT

STAGE CONFIGURATION

The input stage of the ADAS1000/ADAS1000-1/ADAS1000-2

can be arranged in several different manners. The input amplifi-

ers are differential amplifiers and can be configured to generate

the leads in the analog domain, before the ADCs. In addition

to this, the digital data can be configured to provide either

electrode or lead format under user control as described in

Table 37. This allows maximum flexibility of the input stage

for a variety of applications.

Analog Lead Mode and Calculation

Leads are configured in the analog input stage when CHCONFIG

= 1, as shown in Figure 58. This uses a traditional in-amp structure

where lead formation is performed prior to digitization, with

WCT created using the common-mode amplifier. While this

results in the inversion of Lead II in the analog domain, this is

digitally corrected so output data have the proper polarity.

Digital Lead Mode and Calculation

When the ADAS1000/ADAS1000-1/ADAS1000-2 are configured

for digital lead mode (see the FRMCTL register, Register 0x0A[4],

Table 37), the digital core calculates each lead from the electrode

signals. This is straightforward for Lead I/ Lead II/Lead III.

Calculating V1’ and V2’ requires WCT, which is also computed

internally for this purpose. This mode ignores the common-

mode configuration specified in the CMREFCTL register

(Register 0x05). Digital lead calculation is only available in

2 kHz and 16k Hz data rates (see Figure 59).

Electrode Mode: Single-Ended Input Electrode

Configuration

In this mode, the electrode data are digitized relative to the

common-mode signal, VCM, which can be arranged to be any

combination of the contributing ECG electrodes. Common-

mode generation is controlled by the CMREFCTL register as

described in Table 32 (see Figure 61).

Electrode Mode: Common Electrode A and Electrode B

Configurations

In this mode, all electrodes are digitized relative to a common

electrode, for example, RA. Standard leads must be calculated by

post processing the output data of the ADAS1000/ADAS1000-1/

ADAS1000-2 (see Figure 60 and Figure 62).

Figure 57. Electrode and Lead Configurations

MODE

COMMENT

WORD1

WORD2

WORD3

WORD4

WORD5

COMMON

ELECTRODE (CE)

LEADS (HERE RA

ELECTRODE IS

CONNECTED TO THE

CE ELECTRODE

(CM_IN) AND V3 IS ON

ECG3 INPUT)

LEAD I

(LA − RA)

LEAD II

(LL − RA)

V3’

(V3 – RA) − (LA − RA) − (LL − RA)

V1’

(V1 − RA) − (LA − RA) + (LL − RA)

V2’

(V2 − RA) − (LA − RA) + (LL − RA)

ANALOG LEAD

LEAD I

(LA − RA)

LEAD II

(LL − RA)

LEAD III

(LL − LA)

V1’

(V1 − VCM)

V2’

(V2 − VCM)

SINGLE-ENDED

INPUT ELECTRODE

RELATIVE TO VCM

LL − VCM

LEADS FORMED

RELATIVE TO A

COMMON

ELECTRODE (CE)

LA − CE

LL − CE

V1 − CE

V2 − CE

LEAD I

(LA − RA)

LEAD II

(LL − RA)

LEAD III

(LL − LA)

V1’

(V1 − WCT4)

V2’

(V2 − WCT4)

SINGLE-ENDED

INPUT, DIGITALLY

CALCULATED LEADS

COMMON

ELECTRODE A

ANALOG LEAD

SINGLE-ENDED

INPUT

ELECTRODE

COMMON

ELECTRODE B

DIGITAL LEAD

0x0A

[4]1

0x01

[10]2

0x05

[8]3

LA − VCM

V3 − CE

RA − VCM

V1 − VCM

V2 − VCM

1REGISTER FRMCTL, BIT DATAFMT: 0 = LEAD/VECTOR MODE; 1 = ELECTRODE MODE.

2REGISTER ECGCTL, BIT CHCONFIG: 0 = SINGLE ENDED INPUT (DIGITAL LEAD MODE OR ELECTRODE MODE); 1 = DIFFERENTIAL IN PUT (ANALOG LEAD MODE).

3REGISTER CMREFCTL, BIT CEREFEN: 0 = CE DISABLED; 1 = CE ENABLED.

4WILSON CENTRAL TERMINAL (WCT) = (RA + LA + LL)/3, THIS IS A DIGITALLY CALCULATED WCT BASED ON THE RA, LA, LL MEASUREMENTS.

Rev. B | Page 30 of 80

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