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ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

Rev. B | Page 42 of 80

PACING ARTIFACT DETECTION FUNCTION

(ADAS1000 ONLY)

The pacing artifact validation function qualifies potential

pacing artifacts and measures the width and amplitude of valid

pulses. These parameters are stored in and available from any of

the pace data registers (Address 0x1A, and Address 0x3A to

Address 0x3C). This function runs in parallel with the ECG

channels. Digital detection is performed using a state machine

operating on the 128 kHz 16-bit data from the ECG decimation

chain. The main ECG signals are further decimated before

appearing in the 2 kHz output stream so that detected pace

signals are not perfectly time-aligned with fully-filtered ECG

data. This time difference is deterministic and can be

compensated for.

The pacing artifact validation function can detect and

measure pacing artifacts with widths from 100 μs to 2 ms

and with amplitudes of <400 μV to >1000 mV. Its filters are

designed to reject heartbeat, noise, and minute ventilation

pulses. The flowchart for the pace detection algorithm is

shown in Figure 74.

The ADAS1000 pace algorithm can operate with the ac lead-off

and respiration impedance measurement circuitry enabled.

Once a valid pace is detected in the assigned leads, the pace-

detected flags appear in the header word (see Table 54) at the

start of the packet of ECG words. These bits indicate that a pace

is qualified. Further information on height and width of pace is

available by reading the contents of Address 0x1A (PACEDATA

data packet/frame as dictated by the frame control register (see

Table 37). The data available in the PACEDATA register is

limited to seven bits total for width and height information;

therefore, if more resolution is required on the pace height

and width, this is available by issuing read commands of the

PACExDATA registers (Address 0x3A to Address 0x3C) as

shown in Table 53.

The on-chip filtering contributes some delay to the pace signal

(see the Pace Latency section).

Choice of Leads

Three identical and independent state machines are available

and can be configured to run on up to three of four possible

leads (Lead I, Lead II, Lead III, and aVF) for pacing artifact

detection. Any necessary lead calculations are performed

internally and are independent of ECG channel settings for

output data rate, low-pass filter cutoff, and mode (electrode,

analog lead, common electrode). These calculations take into

account the available front-end configurations as detailed in

Table 15.

The pace detection algorithm searches for pulses by analyzing

samples in the 128 kHz ECG data stream. The algorithm

searches for a leading edge, a peak, and a trailing edge as

defined by values in the PACEEDGETH, PACEAMPTH, and

PACELVLTH registers, along with fixed width qualifiers. The

post-reset default register values can be overwritten via the SPI

bus, and different values can be used for each of the three pace

detection state machines.

Some users may not want to use three pace leads for detection.

In this case, Lead II is the vector of choice, because this lead is

likely to display the best pacing artifact. The other two pace

instances can be disabled if not in use.

The first step in pace detection is to search the data stream for a

valid leading edge. Once a candidate edge is detected, the algorithm

begins searching for a second, opposite-polarity edge that meets

with pulse width criteria and passes the (optional) noise filters.

Only those pulses meeting all the criteria are flagged as valid

pace pulses. Detection of a valid pace pulse sets the flag or flags

in the frame header register and stores amplitude and width

information in the PACEDATA register (Address 0x1A; see

Table 44). The pace algorithm looks for a negative or positive pulse.

Table 15. Pace Lead Calculation

0x01 [10]1

0x05 [8]2

Configuration

0x04 [8:3]3

Lead I

(LA − RA)

Lead II

(LL − RA)

Lead III

(LL − LA)

aVF

(Lead II + Lead III)/2

Digital leads

LA – RA

CH1 − CH3

LL – RA

CH2 − CH3

LL – LA

CH2 − CH1

LL − (LA + RA)/2

CH2 − (CH1 + CH3)/2

Common

electrode lead A

Lead I

CH1

Lead II

CH2

Lead II – Lead I

CH2 − CH1

Lead II − 0.5 × Lead I

CH2 − 0.5 × CH1

Analog leads

Lead I

CH1

Lead II

−CH3

Lead III

CH2

Lead II − 0.5 × Lead I − CH3 − 0.5 × CH1

1 Register ECGCTL, Bit CHCONFIG, see Table 28.

2 Register CMREFCTL, Bit CEREFEN, see Table 32.

3 Register PACECTL, Bit PACExSEL [1:0], see Table 31.

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