ADAS1000 datasheet(54/80 Pages) AD

54 / 80 page

ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

SECONDARY SERIAL INTERFACE

This second serial interface is an optional interface that can

be used for the user’s own pace detection purposes. This

interface contains ECG data at 128 kHz data rate only. If using

this interface, the ECG data is still available on the standard

interface discussed previously at lower rates with all the

decimation and filtering applied. If this interface is inactive,

it draws no power.

Data is available in 16-bit words, MSB first.

This interface is a master interface, with the ADAS1000/

ADAS1000-1 providing the SCLK, CS, SDO. Is it shared

across some of the existing GPIO pins as follows:

•

GPIO1/MSCLK

•

GPIO0/MCS

•

GPIO2/MSDO

This interface can be enabled via the GPIO register (see

Table 33).

Figure 81. Master SPI Interface for External Pace Detection Purposes

The data format of the frame starts with a header word and five

ECG data-words, as shown in Table 25, and completes with the

same CRC word as documented in Table 24 for the 128 kHz

rate. All words are 16 bits. MSCLK runs at approximately

20 MHz and MCS is asserted for the entire frame with the data

available on MSDO on the falling edge of MSCLK. MSCLK

idles high when MCS is deasserted.

The data format for this interface is fixed and not influenced by

the FRMCTL register settings. All seven words are output, even

if the individual channels are not enabled.

The header word consists of four bits of all 1s followed by a

12-bit sequence counter. This sequence counter increments

after every frame is sent, thereby allowing the user to tell if

any frames have been missed and how many.

RESET

There are two methods of resetting the ADAS1000/ADAS1000-1/

ADAS1000-2 to power-on default. Bringing the RESET line low

or setting the SWRST bit in the ECGCTL register (Table 28)

resets the contents of all internal registers to their power-on

reset state. The falling edge of the RESET pin initiates the reset

process; DRDY goes high for the duration, returning low when

the RESET process is complete. This sequence takes 1.5 ms

maximum. Do not write to the serial interface while DRDY is

high handling a RESET command. When DRDY returns low,

normal operation resumes and the status of the RESET pin is

ignored until it goes low again. Software reset using the SWRST

bit (see Table 28) requires that a NOP (no operation) command

be issued to complete the reset cycle.

PD FUNCTION

The PD pin powers down all functions in low power mode.

The digital registers maintain their contents. The power-down

function is also available via the serial interface (ECG control

Table 25. Master SPI Frame Format; All Words are 16 Bits

Mode/Word

Electrode mode1

Header

ECG1_LA

ECG2_LL

ECG3_RA

ECG4_V1

ECG5_V2

CRC

Analog lead mode1

Header

LEAD I

LEAD III

-LEAD II (RA-LL)

V1’

V2’

CRC

As set by the FRMCTL register data DATAFMT, Bit [4], see Table 37.

ADAS1000

MASTER SPI

SCLK

MCS/GPIO0

MICROCONTROLLER/

DSP

MSDO/GPIO2

MISO/GPIO

MSCLK/GPIO1

Rev. B | Page 54 of 80

ADAS1000 Datasheet(PDF) 54 Page - Analog Devices

ADAS1000 Datasheet(HTML) 54 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL