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ADAS1000 Datasheet(PDF) 67 Page - Analog Devices |
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ADAS1000 Datasheet(HTML) 67 Page - Analog Devices |
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67 / 80 page ![]() Data Sheet ADAS1000/ADAS1000-1/ADAS1000-2 Table 41. Pace Edge Threshold Register (PACEEDGETH) Address 0x0E, Reset Value = 0x0000001 R/W Default Bit Name Function R/W 0 [23:16] PACE3EDGTH Pace edge trigger threshold R/W 0 [15:8] PACE2EDGTH 0 = PACEAMPTH/2 R/W 0 [7:0] PACE1EDGTH 1 = VREF/GAIN/216 N = N × VREF/GAIN/216 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 42. Pace Level Threshold Register (PACELVLTH) Address 0x0F, Reset Value = 0x0000001 R/W Default Bit Name Function R/W 0 [23:16] PACE3LVLTH[7:0] Pace level threshold; this is a signed value R/W 0 [15:8] PACE2LVLTH[7:0] −1 = 0xFF = −VREF/GAIN/216 R/W 0 [7:0] PACE1LVLTH[7:0] 0 = 0x00 = 0 V +1 = 0x01 = +VREF/GAIN/216 N = N × VREF/GAIN/216 1 ADAS1000 model only, ADAS1000-1/ADAS1000-2 models do not contain these features. Table 43. Read Electrode/Lead Data Registers (Electrode/Lead) Address 0x11 to 0x15, Reset Value = 0x0000001 R/W Default Bit Name Function [31:24] Address [7:0] 0x11: LA or Lead I. 0x12: LL or Lead II. 0x13: RA or Lead III. 0x14: V1 or V1’. 0x15: V2 or V2’. R 0 [23:0] ECG data Channel data value. Data left justified (MSB) irrespective of data rate. The input stage can be configured into different modes (electrode, analog lead, or digital lead) as shown in Table 11. In electrode mode and analog lead mode, the digital result value is an unsigned integer. In digital lead/vector mode, the value is a signed twos complement integer format and has a 2× range compared to electrode format because it can swing from +VREF to –VREF; therefore, the LSB size is doubled. Electrode mode and analog lead mode: Minimum value (000…) = 0 V Maximum value (1111….) = VREF/GAIN LSB = (2 × VREF/GAIN)/(2N– 1) ECG (voltage) = ECG Data × (2 × VREF/GAIN)/(2N– 1) Digital lead mode: Minimum value (1000…) = −(VREF/GAIN) Maximum value (0111….) = +VREF/GAIN LSB = (4 × VREF/GAIN)/(2N – 1) ECG (voltage) = ECG Data × (4 × VREF/GAIN)/(2N – 1) where N = number of data bits: 16 for 128 kHz data rate or 24 for 2 kHz/16 kHz data rate. 1 If using 128 kHz data rate in frame mode, only the upper 16 bits are sent. If using the 128 kHz data rate in regular read/write mode, all 32 bits are sent. Rev. B | Page 67 of 80 |
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