Si3050 datasheet(79/128 Pages) SILABS

79 / 128 page

Si3050 + Si3011/18/19

Rev. 1.5

Reset settings = 1001_0110

Bit

D7D6D5D4D3D2D1D0

Name

RDLY[1:0]

RMX[5:0]

Type

R/W

Bit

Name

Function

7:6

RDLY[1:0]

Ring Delay Bits 1 and 0.

These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time

between when a ring signal is validated and when a valid ring signal is indicated.

RDLY[2]

RDLY[1:0]

Delay

000

0 ms

001

256 ms

010

512 ms

...

111

1792 ms

5:0

RMX[5:0]

Ring Assertion Maximum Count.

These bits set the maximum ring frequency for a valid ring signal within a 10% margin of

error. During ring qualification, a timer is loaded with the RAS[5:0] field upon a TIP/RING

event and decrements at a regular rate. When a subsequent TIP/RING event occurs, the

timer value is compared to the RMX[5:0] field and if it exceeds the value in RMX[5:0] then

the frequency of the ring is too high and the ring is invalidated. The difference between

RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-

ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically

occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every 1/

(2 x 20 Hz) = 25 ms. To calculate the correct RMX[5:0] value for a frequency range [f_min,

f_max], the following equation should be used:

To compensate for error margin and ensure a sufficient ring detection window, it is recom-

mended that the calculated value of RMX[5:0] be incremented by 1.

RMX 5:0



RAS 5:0



2 f_max



2 ms



--------------------------------------------- RMX RAS





–



Si3050 Datasheet(PDF) 79 Page - Silicon Laboratories

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