Si3050 datasheet(10/128 Pages) SILABS

10 / 128 page

Si3050 + Si3011/18/19

Rev. 1.5

Figure 2. General Inputs Timing Diagram

Table 6. Switching Characteristics—General Inputs

(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)

Parameter1

Symbol

Min

Typ

Max

Unit

Cycle Time, PCLK

0.12207

—

3.90625



PCLK Duty Cycle

tdty

PCLK Jitter Tolerance

tjitter

——

Rise Time, PCLK

——

Fall Time, PCLK

——

PCLK Before RESET 2

tmr

—

cycles

RESET Pulse Width3

trl

250

—

CS, SCLK Before RESET

tmxr

—

Rise Time, Reset

——

Notes:

1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

2. FSYNC/PCLK relationship must be fixed after RESET

3. The minimum RESET pulse width is the greater of 250 ns or 10 PCLK cycle times.

PCLK

tmr

VIH

t rl

RESET

tmxr

CS, SCLK

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