Si3050 datasheet(27/128 Pages) SILABS

27 / 128 page

Si3050 + Si3011/18/19

Rev. 1.5

When the HBE bit is cleared, it produces a dc offset that

affects the signal swing of the transmit signal. Silicon

Laboratories recommends that the transmit signal be

12 dB lower than normal transmit levels. A lower level

eliminates clipping from the dc offset that results from

disabling the hybrid. It is assumed in this test that the

line ac impedance is nominally 600 

Note: All test modes are mutually exclusive. If more than one

test mode is enabled concurrently, the results are

unpredictable.

5.8. Exception Handling

The Si3050 can determine if an error occurs during

operation. Through the secondary frames of the serial

link, the controlling DSP can read several status bits.

The bit of highest importance is the frame detect bit

(FDT, Register 12, bit 6) which indicates that the

system-side (Si3050) and line-side (Si3011, 3018 or

Si3019) devices are communicating. During normal

operation, the FDT bit can be checked before reading

the bits that indicate information about the line side. If

FDT is not set, the following bits related to the line side

are invalid—RDT, RDTN, RDTP, LCS[4:0], LSID[1:0],

REVB[3:0], LVS[7:0], LCS2[7:0], ROV, BTD, DOD, and

OVL; the RGDT operation is also non-functional.

Following powerup and reset, the FDT bit is not set

because the PDL bit (Register 6 bit 4) defaults to 1. In

this state, the ISOcap is not operating and no

information about the line side can be determined. The

user must provide a valid PCLK and FSYNC to the

system and clear the PDL bit to activate the ISOcap

link. Communication with the line-side device takes less

than 10 ms to establish.

5.9. Revision Identification

The Si3050 provides information to determine the

revision of the Si3050 and/or the Si3011/18/19. The

REVA[3:0] bits (Register 11) identify the revision of the

Si3050, where 0101b denotes revision E. The

REVB[3:0] bits (Register 13) identify the revision of the

line-side device, where 0110b denotes revision F.

5.10. Transmit/Receive Full-Scale Level

The Si3050 supports programmable maximum transmit

and receive levels. The default signal level supported by

the Si3050 is 0 dBm into a 600  load. Two additional

modes of operation offer increased transmit and receive

level capability to enable use of the DAA in applications

that require higher signal levels. The full-scale mode is

enabled by setting the FULL bit in Register 31. With

FULL = 1 (Si3019 only), the full-scale signal level

increases to +3.2 dBm into a 600  load or 1 dBV into

all reference impedances. The enhanced full-scale

mode (or 2x full scale) is enabled by setting the FULL2

bit in Register 30. With FULL2 = 1, the full-scale signal

level increases to +6.0 dBm into a 600  load or

1.5 dBV into all reference impedances. The full-scale

and enhanced full-scale modes provide the ability to

trade off TX power and TX distortion for a peak signal.

By using the programmable digital gain registers in

conjunction with the enhanced full-scale signal level

mode, a specific power level (+3.2 dBm for example)

can be achieved across all ACT settings.

5.11. Parallel Handset Detection

The Si3050 can detect a parallel handset going

off-hook. When the Si3050 is off-hook, the loop current

can be monitored with the LCS or LCS2 bits. A

significant drop in loop current signals a parallel handset

going off-hook. If a parallel handset going off-hook

causes the loop current to drop to 0, the LCS and LCS2

bits will read all 0s. Additionally, the Drop-Out Detect

(DOD) bit will fire (and generate an interrupt if the

DODM bit is set) indicating that the line-derived power

supply has collapsed.

With the Si3019 line side, the LVS bits also can be read

when on- or off-hook to determine the line voltage.

Significant drops in line voltage can signal a parallel

handset. For the Si3050 to operate in parallel with

another handset, the parallel handset must have a

sufficiently high dc termination to support two off-hook

DAAs on the same line. Improved parallel handset

operation can be achieved by changing the dc

impedance from 50  to 800  and reducing the DCT

pin voltage with the DCV[1:0] bits.

5.12. Line Voltage/Loop Current Sensing

The Si3050 can measure loop current with either the

Si3011, Si3018 or the Si3019 line-side device. The 5-bit

LCS[4:0] register reports loop current measurements

when off-hook. The Si3011 and Si3019 offer an

additional register to report loop current to a finer

resolution (LCS2[7:0]). The Si3050 can only measure

line voltage when used with the Si3011 and Si3019

line-side devices. The LVS[7:0] register is available with

the Si3011 or Si3019, and monitors voltage both on and

off-hook. These registers can be used to help determine

the following line conditions:



When on-hook, detect if a line is connected.



When on-hook, detect if a parallel phone is off-hook.



When off-hook, detect if a parallel phone goes on or

off-hook.



Detect if enough loop current is available to operate.



When used in conjunction with the OPD bit, detect if

an overload condition exists. (See "5.26. Overload

Detection" on page 37.)

Si3050 Datasheet(PDF) 27 Page - Silicon Laboratories

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