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CS5530A Datasheet(PDF) 250 Page - National Semiconductor (TI) |
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CS5530A Datasheet(HTML) 250 Page - National Semiconductor (TI) |
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250 / 259 page  www.national.com 250 Revision 1.1 Electrical Specifications (Continued) Table 5-16. Display Miscellaneous Characteristics Symbol Parameter Min Typ Max Units Comments White Level Relative to Black 16.74 17.62 18.50 mA IAVDD AVDD Supply Current 60 mA (Static) Table 5-17. CRT, TFT/TV and MPEG Display Timing Symbol Parameter Min Typ Max Units Comments (Note 1) Setup/Hold Time tDisplaySetup Display Setup to Rising PCLK: VSYNC, HSYNC, ENA_DISP, FP_VSYNC, FP_HSYNC, PIXEL[23:0] 2.2 ns See Figure 5-1 on page 243. tDisplayHold Display Hold from Rising PCLK: VSYNC, HSYNC, ENA_DISP, FP_VSYNC, FP_HSYNC, PIXEL[23:0] 1.0 ns tVID_VALSetup VID_VAL Setup to Rising VID_CLK 3.0 ns See Figure 5-1 on page 243. tVID_VALHold VID_VALHoldfromRising VID_CLK 0.8 ns tVID_DATASetup VID_DATA Setup to Rising VID_CLK 3.0 ns See Figure 5-1 on page 243, Note 2 tVID_DATAHold VID_DATA Hold from Rising VID_CLK 0.8 ns Clock Specification tVID_CLKMin VID_CLK Minimum Clock Period 7.4 ns Delay Time FPOUTMinDelay, FPOUTMaxDelay TFT/TV Output Delays from FP_CLK: FP_DATA[17:0], FP_HSYNC_OUT, FP_VSYNC_OUT, FP_DISP_ENA_OUT, FP_ENA_VDD, FP_ENA_BKL, FP_CLK_EVEN 0.5 4.5 ns Note 3 VID_RDYMinDelayE, VID_RDYMaxDelayE VID_RDY Delay from Falling VID_CLK (early mode) 3.0 10.5 ns Note 4 VID_RDYMinDelayN, VID_RDYMaxDelayN VID_RDY delay from rising VID_CLK (normal mode) 3.0 9.5 ns 1. All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0°C to 85°C, and CL =50 pF. 2. Also applies to PIXEL[23:16] when in 16-bit video mode. 3. All flat panel applications use the falling edge of FP_CLK to latch their data. 4. The mode for VID_RDY (early or normal) is set with bit 25 of the Video Configuration Register (F4BAR+Memory Offset 00h[25]). |
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