CS5530A datasheet(253/259 Pages) NSC

253 / 259 page

Revision 1.1

253

www.national.com

6.0

Test Mode Information

The CS5530A provides two test modes:

The NAND tree test mode for board-level automatic

test equipment (ATE).

The I/O test mode for system design testing.

6.1

NAND TREE TEST MODE

The NAND tree mode is used to test input and bidirectional

pins which will be part of the NAND tree chain. Table 6-1

shows how to set the device for the NAND tree test.

The output of the NAND tree is multiplexed on the SUSP#

output (pin K26). After a POR# (pin K24) pulse, all inputs in

Table 6-2 on page 254 are initialized to a “1” and then are

successively pulled and held to a “0” starting with

SUSP_3V (the first input pin in the tree). The output wave-

form on SUSP# will toggle on each input change as shown

in Figure 6-1.

POR# is included as an input during the NAND Tree test,

after being used to trigger the test first. IRQ7 (pin AD14)

and TEST (pin D3) must be held high throughout the test.

Figure 6-1. NAND Tree Output Waveform

Table 6-1. NAND Tree Test Selection

Signal Name

Pin No.

Setting

POR#

K24

0 -> 1

TEST

IRQ7

AD14

Initial Conditions: TEST = 1, IRQ7 = 1, POR# = (first 0, then 1), all inputs ‘1’

SUSP_3V

SUSPA#

PSERIAL

CLK_14MHZ

SUSP# (out)

NAND Tree Inputs

NAND Tree Output

Example: Beginning of NAND Tree Test Sequence

The following pins are not in the NAND tree: AEN, BALE, CPU_RST, DACK[3:0]#, DACK[7:5]#, DCLK, DDC_SCL,

D+_PORT1, D–_PORT1, D+_PORT2, D–_PORT2, EXTVREFIN, FP_CLK, FP_CLK_EVEN, FP_DISP_ENA_OUT,

FP_ENA_BKL,

FP_ENA_VDD,

FP_HSYNC_OUT,

FP_VSYNC_OUT,

GPCS#,

GPORT_CS#,

HSYNC_OUT,

IDE_ADDR[2:0], IDE_CS[1:0]#, IDE_DACK[1:0]#, IDE_IOR[1:0]#, IDE_IOW[1:0]#, IDE_RST#, IOUTB, IOUTG,

IOUTR,

IREF,

IRQ7,

ISACLK,

KBROMCS#,

PC_BEEP,

PCI_RST#,

PLLTEST,

SA_LATCH,

SDATA_OUT,

SMEMR#/RTCALE, SMEMW#/RTCCS#, SUSP#, SYNC, TEST, VID_RDY, VSYNC_OUT, all NCs, and all analog/digi-

tal supplies.

CS5530A Datasheet(PDF) 253 Page - National Semiconductor (TI)

CS5530A Datasheet(HTML) 253 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL