CS5530A datasheet(255/259 Pages) NSC

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Test Mode Information (Continued)

6.2

I/O TEST

This test affects all output and bidirectional pins. To trigger

the I/O test, set the TEST and IRQ[3:7] pins according to

Table 6-3, while holding POR# low. The test begins when

POR# is brought high. Starting with the next rising edge of

PCICLK, the states listed in Table 6-4 are entered by all

digital output and I/O pins on successive PCICLK pulses:

The following pins are INCLUDED in this test:

• AD[31:0], AEN, BALE, C/BE[3:0]#, CLK_32K,

CPU_RST, DACK[7:5,3:0], DDC_SCL, DDC_SDA,

DEVSEL#, FP_CLK, FP_CLK_EVEN, FP_DATA[17:0],

FP_DISP_ENA_OUT, FP_ENA_BKL, FP_ENA_VDD,

FP_HSYNC_OUT, FP_VSYNC_OUT, FRAME#,

GPCS#, GPIO[7:0], GPORT_CS#, HOLD_REQ#,

HSYNC_OUT, IDE_ADDR[2:0], IDE_CS[1:0]#,

IDE_DACK[1:0]#, IDE_DATA[15:0], IDE_IOR[1:0]#,

IDE_IOW[1:0]#, IDE_RST#, INTR, IOCHRDY, IOR#,

IOW#, IRDY#, ISACLK, KBROMCS#, LOCK#,

MEMCS16#, MEMR#, MEMW#, PAR, PCI_RST#,

PC_BEEP, PERR#, POWER_EN, REQ#, SA/SD[15:0],

SA[19:16], SA_LATCH, SBHE#, SDATA_OUT, SERR#,

SMEMR#, SMEMW#, SMI#, STOP#, SUSP#,

SUSP_3V, SYNC, TC, TRDY#, VID_RDY, VSYNC_OUT

Note:

The SA/SD and SA bus, IOR#, IOW#, MEMR#,

MEMW# and SBHE# pins never actually float,

because they have internal weak pull-up devices

that remain active.

The following pins are EXCLUDED from this test:

• Input-only pins: BIT_CLK, CLK_14MHZ, DRQ[7:5,3:0],

ENA_DISP, FP_HSYNC, FP_VSYNC, GNT#, HSYNC,

IDE_DREQ[1:0], IDE_IORDY[1:0], INTA#, INTB#,

INTC#, INTD#, IOCS16#, IRQ1, IRQ[7:3], IRQ8#,

IRQ[15:9], OVER_CUR#, PCICLK, PCLK, PIXEL[23:0],

POR#, PSERIAL, SDATA_IN, SUSPA#, TEST, TVCLK,

USBCLK, VID_CLK, VID_DATA[7:0], VID_VAL, VSYNC,

ZEROWS#.

• USB pins: D+_PORT1, D–_PORT1, D+_PORT2,

D–_PORT2, AVDD_USB, AVSS_USB.

• Time-critical output: DCLK.

• Analog pins (including supplies): EXTVREFIN, IOUTB,

IOUTG, IOUTR, IREF, PLLAGD, PLLDGN, PLLDVD,

PLLTEST, AVDDx,AVSSx.

• Digital supply pins (VDD,VSS) and No Connects (NC).

Table 6-3. I/O Test Selection

Signal Name

Pin No.

Setting

POR#

K24

TEST

IRQ3

AC14

IRQ4

AE15

IRQ5

AE13

IRQ6

AF14

IRQ7

AD14

Table 6-4. I/O Test Sequence

Clock #

Output Pin States

Before 1

Undefined

1Floating

2High

3Low

4Floating

5Low

6High

7Floating

8 and beyond

Undefined

CS5530A Datasheet(PDF) 255 Page - National Semiconductor (TI)

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