CS5530A datasheet(258/259 Pages) NSC

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258

Revision 1.1

Support Documentation (Continued)

Table A-2. Edits to Create Revision 1.1

Section

Description

Section 2.0 "Signal Definitions"

Section 2.2.2 "Clock

Interface"

• Changed last sentence of DCLK signal description on page 23.

Did say: “However, system constraints limit DCLK to 150 MHz when DCLK is used as the

graphics subsystem clock.”

Now says: “However, when DCLK is used as the graphics subsystem clock, the Geode

processor determines the maximum DCLK frequency.”

Section 2.2.11 "Dis-

play Interface"

• Changed resistor value in IREF signal description (from 732 ohm to 680 ohm) on page 36.

Section 3.8 "Display Subsystem Extensions"

Section 3.8.3 "Video

Overlay"

• Added sentence to last paragraph on page 135:

— “However, system maximum resolution is not determined by the CS5530A since it is not

the source of the graphics data and timings.”

• Section 3.8.5.3 "Flat Panel Support" on page 137

— Added subsection titled “Flat Panel Power-Up/Down Sequence“.

Section 5.0 "Electrical Specifications"

Section 5.5 "AC Char-

acteristics"

• Table 5-8 "AC Characteristics" on page 242:

— Removed 8 mA, DOTCLK, and FP_CLK tLH and tHL parameters.

• Table 5-10 "DCLK PLL Specifications" on page 246:

— Removed Jitter, Sigma One parameter from table (completely).

• Table 5-11 "CPU Interface Timing" on page 246:

— Changed tSMI maxvalue from 9nsto16ns.

— Changed tSUSPAHold minvalue from 1nsto3 ns.

• Table 5-15 "CRT Display Analog (DAC) Characteristics" on page 249:

— Added VOM max value of 0.735V.

— Added VOC max value of 20 mA.

— Added tFS max value of 2.5 ns.

— Removed COUT parameter from table (completely).

— Changed tRISE max value from 3 to 3.8 ns.

— Added tFALL max value of 3.8 ns.

— Changed RSET value in Note 2 from 732 ohms to 680 ohms.

• Table 5-17 "CRT, TFT/TV and MPEG Display Timing" on page 250:

— Changed tDisplaySetup min value from 2.5 ns to 2.2 ns.

— Changed tVID_VALSetup min value from 3.75 ns to 3.0 ns.

— Changed tVID_VALHold min value from 0 ns to 0.8 ns.

— Changed tVID_DATASetup min value from 3.75 ns to 3.0 ns.

— Changed tVID_DATAHold min value from 0 ns to 0.8 ns.

— Changed tVID_CLKMin parameter description from “VID_CLK Minimum Pulse Width” to

“VID_CLK Minimum Clock Period”.

— Changed FPOUTMinDelay,FPOUTMaxDelay min value from 0.1 ns to 0.5 and max value

from 5.2 ns to 4.5 ns.

CS5530A Datasheet(PDF) 258 Page - National Semiconductor (TI)

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