CS5530A datasheet(246/259 Pages) NSC

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246

Revision 1.1

Electrical Specifications (Continued)

Figure 5-7. CPU Interface Timing

Table 5-10. DCLK PLL Specifications

Symbol

Parameter

Min

Typ

Max

Units

Comments (Note 1)

fDCLK

DCLK Clock Operating Frequency

157.5

MHz

Also known as CRT

clock

fREF

Input Reference Frequency

14.318

MHz

tRISE/FALL

Output Clock Rise/Fall Time

@ 25 MHz

Jitter, Peak-to-Peak

-300

300

Duty Cycle

40/60

60/40

All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0°C to 85°C, and CL =50 pF.

Table 5-11. CPU Interface Timing

Symbol

Parameter

Min

Max

Units

Comments (Note 1)

tSMI

Rising PCICLK to SMI#

tSUSP#

Rising PCICLK to SUSP#

tSUSPASetup

SUSPA# Setup to Rising PCICLK

tSUSPAHold

SUSPA# Hold from Rising PCICLK

IRQ13 Input

Asynchronous input for IRQ decode.

INTR Output

Asynchronous output from IRQ decode.

SMI# Output

Asynchronous output from SMI decode.

All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0°C to 85°C, and CL =50 pF.

PCICLK

SMI#

tSMI

SUSP#

Valid Input

tSUSPAsetup

tSUSPAhold

SUSPA#

tSUSP

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