CS5530A datasheet(245/259 Pages) NSC

245 / 259 page

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Electrical Specifications (Continued)

Figure 5-6. 3.3V PCICLK Waveform

Table 5-9. Clock and Reset Specifications

Symbol

Parameter

Min

Max

Duty

Cycle

Unit

Comments (Note 1)

Output Signals

DCLK Frequency

157.5

40/60

MHz

Note 2

CLK_32K Frequency

32.768

50/50

kHz

Note 3

ISACLK Frequency

8.33333

MHz

Input Signals

CLK_14MHZ Frequency

14.31818

45/55

MHz

USBCLK Frequency

MHz

TVCLK Frequency

MHz

VID_CLK Frequency

135

MHz

tCYC

PCICLK Cycle Time

Note 4

tHIGH

PCICLK High Time

tLOW

PCICLK Low Time

PCICLK Slew Rate

V/ns

See Figure 5-1 on page 243

and Figure 5-5 on page 244

(known as slewr/slewf), Note 5,

and Note 6

PCI_RST# Slew Rate

mV/ns

Rising edge only (deasser-

tion), Note 6

All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0°C to 85°C, and CL =50 pF.

Worst case duty cycle. Duty cycle is a function of PLL post divider. DCLK is programmable to standard video frequen-

cies. Typical jitter < 650 ps peak-to-peak. CLK_14MHZ input jitter < 500 ps peak-to-peak.

CLK_32K jitter = period of CLK_14MHZ. CLK_32K output frequency = CLK_14MHZ/436.95621.

Frequency of operation is from DC to 33 MHz but at a single fixed frequency. Operation below 20 MHz is guaranteed by

design.

Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the

minimum peak-to-peak portion of the clock waveform as shown in Figure 5-6.

Not 100% tested.

0.3 VDD

0.4 VDD

0.5 VDD

tHIGH

0.6 VDD

tLOW

0.2 VDD

tCYC

0.4 VDD, peak-to-peak

(minimum)

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