CS5530A datasheet(242/259 Pages) NSC

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242

Revision 1.1

Electrical Specifications (Continued)

5.5

AC CHARACTERISTICS

The following tables list the AC characteristics including

output delays, input setup requirements, input hold require-

ments and output float delays. The rising-clock-edge refer-

ence level, VREF, and other reference levels are shown in

Table 5-7. Input or output signals must cross these levels

during testing.

Input setup and hold times are specified minimums that

define the smallest acceptable sampling window for which

a synchronous input signal must be stable for correct opera-

tion.

Table 5-7. Drive Level and Measurement Points

for AC Characteristics

Symbol

Voltage (V)

VREF

1.5

VDD

3.14

VSS

Table 5-8. AC Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Comments (Note 1)

tSU

Input Setup Time to PCICLK

See Figures 5-1 and 5-2 on

page 243

Input Hold Time to PCICLK

tLH

Low to High Propagation Delay (Referenced to PCICLK, Note 2)

PCI

See Figure 5-2 on page 243 and

Figure 5-3 on page 244 (also

known as tVAL)

tHL

High to Low Propagation Delay (Referenced to PCICLK, Note 2)

PCI

See Figure 5-2 on page 243 and

Figure 5-4 on page 244 (also

known as tVAL)

tRISE/FALL

Rising/Falling Edge Rate

IDE

1.25

V/ns

See Figures 5-1 and 5-2 on

page 243, Note 3

All tests, unless otherwise specified, are at VDD = 3.14V to 3.46V, TC = 0°C to 85°C, and CL =50 pF.

Pins with this buffer type are listed in Table 2-3 "352 PBGA Pin Assignments - Sorted Alphabetically by Signal Name"

on page 19.

Not 100% tested.

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