CS5530A datasheet(240/259 Pages) NSC

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240

Revision 1.1

Electrical Specifications (Continued)

5.4.1

Definition of System Conditions for Measuring “On” Parameters

The current of the CS5530A is highly dependent on the

DCLK (DOT clock). Table 5-5 shows how these factors are

controlled when measuring the typical average and abso-

lute maximum CS5530A current parameters. Table 5-6 pro-

vides

the

CS5530A’s

core,

DAC,

and

PLL

characteristics during various power states.

Table 5-5. System Conditions Used to Determine CS5530A’s Current Used During the “On” State

CPU Current Measurement

System Conditions

VDD (Note 1)

DCLK Frequency (Note 2)

Typical Average

Nominal

50 MHz (Note 3)

Absolute Maximum

Max

135 MHz (Note 4)

See Table 5-3 on page 237 for nominal and maximum voltages.

Not all system designs support display modes that require a DCLK of 157 MHz. Therefore, absolute maximum current

will not berealizedinall system designs.

A DCLK frequency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz, using a display image

of vertical stripes (4-pixel wide) alternating between black and white with power management disabled.

A DCLK frequency of 157 MHz is derived by setting the display mode to 1280x1024x8 bpp at 85 Hz, using a display

image of vertical stripes (1-pixel wide) alternating between black and white with power management disabled.

CS5530A Datasheet(PDF) 240 Page - National Semiconductor (TI)