CS5530A datasheet(241/259 Pages) NSC

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Electrical Specifications (Continued)

Table 5-6. DC Characteristics During Power States

Symbol

Parameter

Min

Typ

Max

Units

Comments

Core (Note 1)

IDD_CORE

Active IDD

145

255

Note 2 and Note 3

IDDAI_CORE

Active Idle IDD

Note 4

IDDSM_CORE

SuspendModeIDD

Note 5

IDDSS_CORE

Standby IDD

5.7

Note 6

DAC (Note 1)

IDD_DAC

Active IDD

Note 2 and Note 3

IDDAI_DAC

Active Idle IDD

Note 4

IDDSM_DAC

SuspendModeIDD

0.2

Note 5

IDDSS_DAC

Standby IDD

0.2

Note 6

PLL (Note 1)

IDD_PLL

Active IDD

IDDAI_PLL

Active Idle IDD

6mA

Note 4

IDDSM_PLL

SuspendModeIDD

0.3

Note 5

IDDSS_PLL

Standby IDD

0.2

Note 6

EXTVREFIN

IDD_EXTVREFIN

Active IDD

µA

Outputs unloaded.

Maximum current is measured under the following assumptions:

PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 157 MHz, and VID_CLK = 133 MHz.

Typical current is measured under the following assumptions:

PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 50 MHz, and VID_CLK = 0 MHz.

Active Idle current is measured under the following assumptions with SUSPA# asserted:

PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 50 MHz, and VID_CLK = 0 MHz.

Suspend current is measured under the following assumptions with SUSPA# asserted:

PCICLK = 33 MHz, USBCLK = 48 MHz, DCLK = 0 MHz, and VID_CLK = 0 MHz.

Standby current is measured under the following assumptions with SUSPA# and SUSP_3V (stop clock signal) asserted:

PCICLK = 0 MHz, USBCLK = 0 MHz, DCLK = 0 MHz, and VID_CLK = 0 MHz.

CS5530A Datasheet(PDF) 241 Page - National Semiconductor (TI)

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