TMP117 datasheet(17/45 Pages) TI1

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I/O

Control

Interface

SCL

SDA

Temperature

Configuration

LOW

EEPROM1 to 4

Pointer

HIGH

TMP117

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SNOSD82 – JUNE 2018

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Programming (continued)

7.5.2 Pointer Register

Figure 20 shows the internal register structure of the TMP117. The 8-bit pointer register of the device is used to

address a given data register. The power-up reset value is 00. By default, the TMP117 reads the temperature on

power-up.

Figure 20. Internal Register Structures

7.5.3 I2C and SMBus Interface

7.5.3.1 Serial Interface

The TMP117 operates as a slave device only on the two-wire, SMBus and I2C interface-compatible bus.

Connections to the bus are made through the open-drain I/O lines and the SDA and SCL pins. The SDA and

SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes

and bus noise. The device supports the transmission protocol for fast (1 kHz to 400 kHz) mode. Register bytes

are sent with the most significant byte first, followed by the least significant byte.

7.5.3.1.1

Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a high-

to low-logic level when the SCL pin is high. All slaves on the bus shift in the slave address byte on the rising

edge of the clock, and the last bit indicates whether a read or write operation is intended. During the ninth clock

pulse, the addressed slave generates an acknowledge and pulls the SDA pin low to respond to the master.

A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data

transfer, the SDA pin must remain stable when the SCL pin is high because any change in the SDA pin when the

SCL pin is high is interpreted as a START or STOP signal.

When all data are transferred, the master generates a repeated START or STOP condition indicated by pulling

the SDA pin from low to high when the SCL pin is high.

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