TMP117 datasheet(19/45 Pages) TI1

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SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

(BUF)

TMP117

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SNOSD82 – JUNE 2018

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7.5.3.1.5

SMBus Alert Function

The TMP117 supports the SMBus alert function. When the ALERT pin is connected to an SMBus alert signal and

a master senses that an alert condition is present, the master can send out an SMBus ALERT command (0001

1001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus ALERT command and

responds by returning the slave address on the SDA line. The eighth bit (LSB) of the slave address byte

indicates if the alert condition is caused by the temperature exceeding T(HIGH) or falling below T(LOW). The LSB is

high if the temperature is greater than T(HIGH), or low if the temperature is less than T(LOW). See Figure 24 for

details of this sequence.

If multiple devices on the bus respond to the SMBus ALERT command, arbitration during the slave address

portion of the SMBus ALERT command determines which device clears the alert status of that device. The

device with the lowest two-wire address wins the arbitration. If the TMP117 wins the arbitration, the TMP117

ALERT pin becomes inactive at the completion of the SMBus ALERT command. If the TMP117 loses the

arbitration, the TMP117 ALERT pin remains active.

7.5.3.1.6

General-Call Reset Function

The TMP117 responds to a two-wire, general-call address (0000 000) if the eighth bit is 0. The device

acknowledges the general-call address and responds to commands in the second byte. If the second byte is

0000 0110, the TMP117 internal registers are reset to power-up values.

7.5.3.1.7

Timeout Function

The TMP117 resets the serial interface if the SCL line is held low by the master or the SDA line is held low by

the TMP117 for 35 ms (typical) between a START and STOP condition. The TMP117 releases the SDA line if

the SCL pin is pulled low and waits for a START condition from the host controller. To avoid activating the

timeout function, maintain a communication speed of at least 1 kHz for the SCL operating frequency.

7.5.3.1.8

Timing Diagrams

The TMP117 is two-wire, SMBus, and I2C interface-compatible. Figure 21 to Figure 25 show the various

operations on the TMP117. Parameters for Figure 21 are defined in Two-Wire Interface Timing. Bus definitions

are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a

START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The TMP117 can also be used for single byte updates. To update only the

MS byte, terminate the communication by issuing a START or STOP communication on the bus.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that

acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line

is stable low during the high period of the acknowledge clock pulse. The user must take setup and hold times

into account. On a master receive, the termination of the data transfer can be signaled by the master generating

a not-acknowledge (1) on the last byte transmitted by the slave.

Figure 21. Two-Wire Timing Diagram

TMP117 Datasheet(PDF) 19 Page - Texas Instruments

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