LTC2662 datasheet(8/28 Pages) AD

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LTC2662

Rev 0

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TIMING CHARACTERISTICS The

denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at TJ = 25°C. Digital input low and high voltages are 0V and IOVCC, respectively.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: Offset current is measured at code 384; Linearity is defined from

code 384 to code 65,535.

Note 4: For IFS = 300mA, RLOAD = 10Ω; IFS = 200mA, RLOAD = 15Ω;

IFS = 100mA, RLOAD = 30Ω; IFS = 50mA, RLOAD = 50Ω; IFS = 25mA,

RLOAD = 100Ω; IFS = 12.5mA, RLOAD = 200Ω; IFS = 6.25mA,

RLOAD = 400Ω; IFS = 3.125mA, RLOAD = 800Ω

Note 5: IFS = 200mA, RLOAD = 15Ω; DC crosstalk is measured with a

100mA to 200mA current step on all 4 aggressor channels. Total Power

Dissipation change is 4 × 50mW = 200mW. Monitor channel is held at 3/4

*IFS or 150mA.

Note 6: DAC-to-DAC crosstalk is the glitch that appears at the output

of one DAC due to a 100mA to 200mA step change in an adjacent DAC

channel. The measured DAC is at mid-scale (100mA). 200mA range,

internal reference, VDDX = 5V, V– = –5V.

Note 7: Temperature coefficient is calculated by first computing the ratio

of the maximum change in output voltage to the nominal output voltage.

The ratio is then divided by the specified temperature range.

Note 8: Guaranteed by design and not production tested.

Note 9: VDDX = 5V (3.125mA range); VDDX = 4V (200mA range); V– = –5V

for all ranges. For large current output steps, internal thermal effects result

in a final settling tail. In most cases the tail is too small to affect settling

to ±0.024%, but several milliseconds may be needed for full settling to the

±0.0015% level. For best results, always solder the exposed pad (pin 33)

to a solid GND plane, and set VDDX as low as practicable for each channel

to reduce power dissipation in the part. The listed results were obtained

using a DC2692 demo circuit with no additional heatsinks.

Note 10: VCC = IOVCC = 5V; VDD0-4 = 5V, V– = –5V.

Note 11: Digital Inputs at 0V or IOVCC.

Note 12: Internal reference mode. Load is 15Ω (200mA range) or 800Ω

(3.125mA range) in parallel with 100pF terminated to GND.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CLR Pulse Width

t10

CS/LD High to SCK Positive Edge

t12

LDAC Pulse Width

t13

CS/LD High to LDAC High or Low Transition

SCK Frequency

50% Duty Cycle

MHz

t14

TGP High Time

(Note 8)

µs

t15

TGP Low Time

(Note 8)

µs

V+ = VDDX = VCC = 2.85V to 5.5V, 1.71V ≤ IOVCC < 2.85V

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK HIGH Time

SCK LOW Time

CS/LD Pulse Width

LSB SCK High to CS/LD High

CS/LD Low to SCK High

SDO Propagation Delay From SCK Falling Edge

CLOAD = 10pF

CLR Pulse Width

t10

CS/LD High to SCK Positive Edge

t12

LDAC Pulse Width

t13

CS/LD High to LDAC High or Low Transition

SCK Frequency

50% Duty Cycle

MHz

t14

TGP High Time

(Note 8)

µs

t15

TGP Low Time

(Note 8)

µs

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