LTC2662 datasheet(17/28 Pages) AD

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LTC2662

Rev 0

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Data Transfer Functions

The DAC input-to-output transfer functions for all resolu-

tions and output ranges greater than or equal to 25mA

are shown in Figure 3. The input code is in straight binary

format for all ranges.

Serial Interface

When the CS/LD pin is taken low, the data on the SDI

pin is loaded into the shift register on the rising edge

of the clock (SCK pin). The 4-bit command, C3-C0, is

loaded first, followed by the 4-bit DAC address, A3-A0,

and finally the 16-bit data word in straight binary format.

For the LTC2662-16, the data word comprises the 16-bit

input code, ordered MSB-to-LSB. Data can only be trans-

ferred to the LTC2662 when the CS/LD signal is low. The

rising edge of CS/LD ends the data transfer and causes

the device to carry out the action specified in the 24-bit

input word.

While the minimum input word is 24 bits, it may option-

ally be extended to 32 bits. To use the 32-bit word width,

8 don’t-care bits must be transferred to the device first,

followed by the 24-bit word, as just described. The 32-bit

word is required for echo read-back and daisy-chain

operation. It also provides accommodation for proces-

sors that have a minimum word width of 16 or more bits.

Figure 3. LTC2662-16 Transfer Function

300mA RANGE

200mA RANGE

100mA RANGE

50mA RANGE

25mA RANGE

CODE

16384

32768

49152

65535

100

150

200

250

300

2662 F03a

OPERATION

The complete 24-bit and 32-bit sequences are shown in

Figure 2a and Figure 2b. Note that the Fault Register out-

puts appear on the SDO pin for either word width.

Input and DAC Registers

The LTC2662 has five internal registers for each DAC, in

addition to the main shift register. Each DAC channel has

two sets of double-buffered registers: one set for the code

data, and one set for the span (output range) of the DAC.

Double buffering provides the capability to simultaneously

update the span and code, which allows smooth current

transitions when changing output ranges. It also permits

the simultaneous updating of multiple DACs.

Each set of double-buffered registers comprises an input

• Input Register: The write operation shifts data from

the SDI pin into a chosen register. The input registers

are holding buffers; write operations do not affect the

DAC outputs

In the code data path, there are two input registers,

A and B, for each DAC register. Register B is an alter-

nate register used only in the toggle operation, while

• DAC Register: The update operation copies the con-

tents of an input register to its associated DAC regis-

ter. The content of a DAC register directly controls the

DAC output current or range. The update operation

also powers up the selected DAC if it had been in

power-down mode.

Note that updates always refresh both code and span

data, but the values held in the DAC registers remain

unchanged unless the associated input register values

have been changed via a write operation. For example,

if a new code is written and the channel is updated, the

code is updated while the span is refreshed unchanged. A

channel update can come from a serial update command,

an LDAC negative pulse or a toggle operation.

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