LTC2662 datasheet(23/28 Pages) AD

23 / 28 page

LTC2662

Rev 0

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OPERATION

select bits as needed to select the input register (A or B)

with which each channel is to be updated. Then update all

channels, either by using the serial command (1001b) or

by applying a negative pulse to the LDAC pin. Any chan-

nels whose toggle select bits are 0 update from input

update from input register B (see Figure 9). By alternating

toggle select and update operations, up to 5 channels can

be simultaneously switched to A or B as needed.

Daisy-Chain Operation

The serial output of the shift register appears at the SDO

pin. Data transferred to the device from the SDI input is

delayed 32 SCK rising edges before being output at the

next SCK falling edge, suitable for clocking into the micro-

processor on the next 32 SCK rising edges.

The SDO output can be used to facilitate control of multi-

ple serial devices from a single 3-wire serial port (i.e. SCK,

SDI and CS/LD). Such a daisy-chain series is configured

by connecting the SDO of each upstream device to the SDI

of the next device in the chain. The shift registers of the

devices are thus connected in series, effectively forming a

single input shift register which extends through the entire

chain. Because of this, the devices can be addressed and

controlled individually by simply concatenating their input

words; the first instruction addresses the last device in

the chain and so forth. The SCK and CS/LD signals are

common to all devices in the series.

In use, CS/LD is first taken low. Then, the concatenated

input data is transferred to the chain, using the SDI of the

first device as the data input. When the data transfer is

complete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the no-operation command

(1111b) for all other devices in the chain. When CS/LD is

taken high, the SDO pin presents a high impedance out-

put, so a pull-up resistor is required at the SDO of each

device (except the last) for daisy-chain operation.

Echo Readback

The SDO pin can be used to verify data transfer to the

device. During each 32-bit instruction cycle, SDO outputs

the previous 32-bit instruction for verification. The 8-bit

“don’t-care” prefix is replaced by 8 Fault Register status

bits, followed by the 4-bit command and address words

and the full 16-bit data word (see Figure 2a). The SDO

sequence for a 24-bit instruction cycle is the same, except

that the data word is truncated to 8 bits (see Figure 2b).

When CS/LD is high, SDO presents a high impedance

output, releasing the bus for use by other SPI devices.

Fault Register (FR)

The LTC2662 provides notifications of operational fault

conditions. The fault register (FR) status bits comprise

the first data byte (8 bits) of each 24- or 32-bit SDO word,

outputted to the SDO pin during every SPI transaction.

See Figure 2 for sequences.

An FR bit is set when its trigger condition is detected,

and clocked to SDO during the next SPI transaction. FR

information is updated with each SPI transaction. Note

that if a fault condition is corrected by the action of an

SPI instruction, the cleared FR flag for that condition is

observable at SDO on the next SPI transaction.

Table 5 lists the Fault Register bits and their associated

trigger conditions.

Table 5. Fault Register (FR)

FR Bit

Fault Condition

FR0

Open-Circuit condition detected on OUT0

FR1

Open-Circuit condition detected on OUT1

FR2

Open-Circuit condition detected on OUT2

FR3

Open-Circuit condition detected on OUT3

FR4

Open-Circuit condition detected on OUT4

FR5

Overtemperature. If die temperature TJ > 175°C, FR5 is

set and thermal protection is activated. Can be disabled

using the Config command (0111b).

FR6

Power Limit. If VDDX - VOUTX > 10V and the current range

is ≥ 200mA, FR6 is set and the range for that channel

is reduced to 100mA. Can be disabled using the Config

command (0111b).

FR7

Invalid SPI sequence length. Valid sequence lengths are

24 and 32 bits. For all other lengths, FR7 is set and the

SPI instruction is ignored.

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