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ES8288 Datasheet(PDF) 8 Page - Suzhou Everest Semiconductor Co. Ltd. |
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ES8288 Datasheet(HTML) 8 Page - Suzhou Everest Semiconductor Co. Ltd. |
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8 / 25 page ![]() Everest Semiconductor ES8288 Revision 6.0 November 2016 8 16 kHz (MCLK/750) 10111 MCLK 22.0588 kHz (MCLK/544) 10110 MCLK 24 kHz (MCLK/500) 10101 MCLK 32 kHz (MCLK/375) 10100* MCLK 44.118 kHz (MCLK/272) 10011 MCLK 44.118 kHz (MCLK/272) 10011 MCLK 48 kHz (MCLK/250) 10010 MCLK 48 kHz (MCLK/250) 10010 MCLK 88.235 kHz (MCLK/136) 10001 MCLK 96 kHz (MCLK/125) 10000 MCLK 5 MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard SPI and 2-wire micro-controller configuration interface. External micro-controller can completely configure the device through writing to internal configuration registers. Please see section 8 for the details of configuration register definition. The identical device pins are used to configure either SPI or 2-wire interface. In SPI mode, pin CE, CCLK and CDATA function as SPI_CSn, SPI_CLK and SPI_DIN. In 2-wire mode, pin CE, CCLK and CDATA function as AD0, SCL and SDA. To select SPI mode, apply high to low transition signal to CE pin. Otherwise the device will operate in 2-wire interface mode. 5.1 SPI ES8288 has a SPI (Serial Peripheral Interface) compliant synchronous serial slave controller inside the chip. It provides the ability to allow the external master SPI controller to access the internal registers, and thus control the operations of chip. All lines on the SPI bus are unidirectional: The SPI_CLK is generated by the master controller and is primarily used to synchronize data transfer, the SPI_DIN line carries data from the master to the slave; SPI_CSn is generated by the master to select ES8288. The timing diagram of this interface is given in Figure 1. The high to low transition at SPI_CSn pin indicates the SPI interface selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal register address and internal register data. Every word length is fixed at 8 bits. The input SPI_DIN data are sampled at the rising edge of SPI_CLK clock. The MSB bit in each word is transferred firstly. The transfer rate can be up to 10M bps. |
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