Everest Semiconductor

ES8288

Revision 6.0

November 2016

13

VSEL

6:0

1111100 – normal (default)

6.1.8

Register 8 – Master Mode Control, Default 1000 0000

Bit Name

Bit

Description

MSC

7

0 – slave serial port mode

1 – master serial port mode (default)

MCLKDIV2

6

0 – MCLK not divide (default)

1 – MCLK divide by 2

BCLK_INV

5

0 – normal (default)

1 – BCLK inverted

BCLKDIV

4:0

00000 – master mode BCLK generated automatically based on the clock table (default)

Others – MCLK/N, N=1~31

6.2

ADC Control

6.2.1

Register 9 – ADC Control 1, Default 0000 0000

Bit Name

Bit

Description

MicAmpL

7:4

Left channel PGA gain

0000 – 0 dB (default)

0001 – +3 dB

0010 – +6 dB

0011 – +9 dB

0100 – +12 dB

0101 – +15 dB

0110 – +18 dB

0111 – +21 dB

1000 – +24 dB

MicAmpR

3:0

Right channel PGA gain

0000 – 0dB (default)

0001 – +3 dB

0010 – +6 dB

0011 – +9 dB

0100 – +12 dB

0101 – +15 dB

0110 – +18 dB

0111 – +21 dB

1000 – +24 dB

6.2.2

Register 10 – ADC Control 2, Default 0000 0000

Bit Name

Bit

Description

LINSEL

7:6

Left channel input select

00 – LINPUT1 (default)

01 – LINPUT2

10 – LINPUT3