Everest Semiconductor

ES8288

Revision 6.0

November 2016

11

Reg. 22

NGTH

NGG

NGAT

Reg. 43

slrck

Lrck_sel

Adc_dll_pwd

6.1

Chip Control and Power Management

6.1.1

Register 0 – Chip Control 1, Default 0000 0110

Bit Name

Bit

Description

SCPReset

7

0 – normal (default)

1 – reset control port register to default

LRCM

6

0 – ALRCK disabled when both ADC disabled; DLRCK disabled when both DAC disabled (default)

1 – ALRCK and DLRCK disabled when all ADC and DAC disabled

SeqEn

3

0 – internal power up/down sequence disable (default)

1 – internal power up/down sequence enable

EnRef

2

0 – disable reference

1 – enable reference (default)

VMIDSEL

1:0

00 – Vmid disabled

01 – 50 k

Ω divider enabled

10 – 500 k

Ω divider enabled (default)

11 – 5 k

Ω divider enabled

6.1.2

Register 1 – Chip Control 2, Default 0001 1100

Bit Name

Bit

Description

TSDEN

7

0 – thermal shutdown disabled (default)

1 – thermal shutdown enabled

PdnOC

6

0 – over current shutdown disabled (default)

1 – over current shutdown enabled

LPVcmMod

5

0 – normal (default)

1 – low power

LPVrefBuf

4

0 – normal

1 – low power (default)

PdnAna

3

0 – normal

1 – entire analog power down (default)

PdnIbiasgen

2

0 – normal

1 – ibiasgen power down (default)

VrefLo

1

0 – normal (default)

1 – low power

PdnVrefbuf

0

0 – normal (default)

1 – power down

6.1.3

Register 2 – Chip Power Management, Default 1100 0011

Bit Name

Bit

Description

adc_DigPDN

7

0 – normal