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ES8288 Datasheet(PDF) 10 Page - Suzhou Everest Semiconductor Co. Ltd.

Part # ES8288
Description  Low Power Stereo Audio ADC
PDF  25 Pages
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Manufacturer  EVEREST [Suzhou Everest Semiconductor Co. Ltd.]
Direct Link  http://www.everest-semi.com/en_index.html
Logo EVEREST - Suzhou Everest Semiconductor Co. Ltd.

ES8288 Datasheet(HTML) 10 Page - Suzhou Everest Semiconductor Co. Ltd.

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Everest Semiconductor
ES8288
Revision 6.0
November 2016
10
Table 3 Write Data to Register in 2-wire Interface Mode
Chip Address
R/W
Register Address
Data to be written
001000
AD0
0
ACK
RAM
ACK
DATA
Table 4 Read Data from Register in 2-wire Interface Mode
Chip Address
R/W
Register Address
001000
AD0
0
ACK
RAM
Chip Address
R/W
Data to be read
001000
AD0
1
ACK
DATA
6
CONFIGURATION REGISTER DEFINITION
SPI and 2-wire configuration interface share the same registers because there
is only one interface active at any time. There are total of 53 user
programmable 8-bit registers in this device. These registers control the
operations of ADC and DAC. External master controller can access these
registers by using the slave address specified in RAM (Register Address Map)
register as shown in the Table 5.
Table 5 Bit Content of Register Address Map
B7
B6
B5
B4
B3
B2
B1
B0
Reg. 00
SCPReset
LRCM
SeqEn
EnRef
VMIDSEL
Reg. 01
TSDEN
PdnOC
LPVcmMod
LPVrefBuf
PdnAna
PdnIbiasgen
VrefrLo
PdnVrefbuf
Reg. 02
adc_DigPDN
adc_stm_rst
ADCDLL_PDN
adcVref_PDN
Reg. 03
PdnAINL
PdnAINR
PdnADCL
PdnADCR
PdnMICB
PdnADCBiasgen
flashLP
int1LP
Reg. 05
OC[2]
OC[3]
Reg. 06
LPPGA
LPADCvrp
Reg. 07
VSEL
Reg. 08
MSC
MCLKDIV2
BCLK_INV
BCLKDIV
Reg. 09
MicAmpL
MicAmpR
Reg. 10
LINSEL
RINSEL
Reg. 11
DS
TRI
OC[1:0]
Reg. 12
DATSEL
ADCLRP
ADCWL
ADCFORMAT
Reg. 13
ADCFsMode
ADCFsRatio
Reg. 14
ADC_invL
ADC_invR
ADC_HPF_L
ADC_HPF_R
Reg. 15 ADCRampRate ADCSoftRamp
ADCZeroCrs
ADCLeR
ADCMute
Reg. 16
LADCVOL
Reg. 17
RADCVOL
Reg. 18
ALCSEL
MAXGAIN
MINGAIN
Reg. 19
ALCLVL
ALCHLD
Reg. 20
ALCDCY
ALCATK
Reg. 21
ALCMODE
ALCZC
TIME_OUT
WIN_SIZE



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