D17133CS datasheet(187/289 Pages) NEC

187 / 289 page

CHAPTER 16

RESET

172

Figure 16-1. Reset Block Configuration

Note The

µPD17P132 and 17P133 have no pull-up resistor by mask option, and are always open.

16.2 RESETTING

Operation when reset is caused by the RESET input is shown in the figure below.

If the RESET pin is set from low to high, system clock generation starts and an oscillation stabilization wait occurs

with the timer. Program execution starts from address 0000H.

If power-on reset function is used, the reset signals shown in Figure 16-2 are internally generated. Operation

is the same as that when reset is caused externally by the RESET input.

At address stack overflow and underflow reset, oscillation stabilization wait time (WAIT a) does not occur.

Operation starts from address 0000H after initial statuses are internally set.

Figure 16-2. Resetting

RESET

TMEN

TMRES

Operationg mode

RESET

WAIT aNote

Operating mode

Note This is oscillation stabilization wait time. Operating mode is set when timer counts system clocks 256

256 time (approx. 8ms, at fX=8 MHz/approx. 32 ms, at fCC=2 MHz)

Internal bus

RF : 10H

PDRESEN

VDD

Clear signal

Mask optionNote

Low-voltage detection circuit

Power-on reset circuit

Internal reset signal

Oscillation

disabled

RESET

D17133CS Datasheet(PDF) 187 Page - NEC