D17133CS datasheet(127/289 Pages) NEC

127 / 289 page

CHAPTER 12

PORTS

112

12.6.1 Cautions when Operating Port Registers

Among the input/output ports in the

µPD17120 series, only port 0E is such that, even when in output mode, doing

a read causes the status of the pins to be read.

Consequently, when executing port register read macro instructions (SETn/CLRn, etc.) or bit manipulation

instructions such as AND/OR/XOR, etc., you may inadvertently change the status of the pins.

Be particularly careful when port 0E is being externally forced down to low level.

Figure 12-1 shows an example of the changes in the port register and microcontroller internal status when the

CLR1 P0E1 instruction (equivalent to the AND 6F, #1101B instruction) is executed.

For example, consider the case where both the P0E1 and P0E0 pins of port 0E are used for output, high level is

output from pins P0E1 and P0E0, and the P0E0 pin is being externally forced down to a low level; then the status

of each pin of port 0E is as shown in Figure 12-1 <1>. The (P0E3 and P0E2 pins do not exist in the

µPD17120 subseries,

but are handled as if they exist in the program.)

If the CLR1 P0E1 instruction is executed to bring the P0E1 pin to low level, the status of each pin of port 0E changes

as shown in Figure 12-1 <2>. In this case, the P0E1 pin naturally changes to output low level, but the value of the

port register changes so that pin P0E0, which should output high level, also outputs low level. This result comes

about because the CLR1 P0E1 instruction is executed not on the port register, but on the state of the pins.

To avoid this phenomenon, use a MOV or other instruction to set the state of all the pins, not just the pins that

are to be changed. In this example, to set just the P0E1 pin to a low level, you can use the MOV 6FH, #1101 instruction,

and the problem will not occur.

For the same reason, when using port 0E for mixed input and output, be sure to put the pins that are being used

for input into input mode (P0EBI0n = 0).

Figure 12-1. Changes in Port Register Due to Execution of the CLR1 P0E1 Instruction

P0E3

–

Does not exist

P0E2

–

P0E1

H output

P0E0

H output

L (forced)

Execution of the CLR1 P0E1

instruction

[AND 6FH, #1101B]

Port register

Microcomputer state

Pin state

<1> Before executing instructions

P0E3

–

Does not exist

P0E2

–

P0E1

L output

P0E0

L output

Port register

Microcomputer state

Pin state

H: high level

L: low level

<2> After executing instructions

D17133CS Datasheet(PDF) 127 Page - NEC

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