D17133CS datasheet(124/289 Pages) NEC

124 / 289 page

CHAPTER 12

PORTS

109

12.5 PORT 0D (P0D0/SCK, P0D1/SO, P0D2/SI, P0D3/TMOUT)

Port 0D is a 4-bit input/output port with an output latch. It is mapped into address 73H of BANK0 in data memory.

The output format is N-ch open-drain output. The mask option can be used to specify that a pin contain a pull-up

resistor bit-by-bit Note.

Input or output can be specified bit-by bit. Input/output is specified with P0DBIO0 to P0DBIO3 (address 33H)

in the register file.

If P0DBIOn is 0 (n=0 to 3), the P0Dn pins are used as input port. Pin statuses are read if a data read instruction

is executed for the port register. If P0DBIOn is 1, the P0Dn pins are used as output port and the value written in

the output latch are output to pins. If a data read instruction is executed when pins are used as output ports, the

output latch value, rather than pin statuses, is fetched.

At reset, P0DBIOn is set to 0 and all P0D pins become input ports. The contents of the port output latch become

0. The output latch contents remain unchanged even if P0DBIOn changes from 1 to 0.

Port 0D can also be used for serial interface input/output or timer output. SIOEN (0AH bit 0) in the register file

is used to switch ports (P0D0 to P0D2) to serial interface input/output (SCK, SO, SI) and vice versa. TMOSEL (bit

0 at address 12H) in the register file is used to switch a port (P0D3) to timer output (TMOUT) and vice versa. If

TMOSEL=1 is selected, 1 is output at timer reset. This output is inverted every time a timer count value matches

the modulo register contents.

Note The

µPD17P132 and 17P133 have no pull-up resistor by mask option.

D17133CS Datasheet(PDF) 124 Page - NEC