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Data Sheet

AD9175

Rev. A | Page 35 of 150

PHYSICAL LAYER

The physical layer of the JESD204B interface, hereafter referred

to as the deserializer, has eight identical channels. Each channel

consists of the termination, an equalizer, a clock and data recovery

(CDR) circuit, and the 1:40 demux function (see Figure 55).

EQUALIZER

CDR

1:40

DESERIALIZER

FROM SERDES PLL

SPI

CONTROL

TERMINATION

SERDINx±

Figure 55. Deserializer Block Diagram

JESD204B data is input to the AD9175 via the SERDINx±

differential input pins, per the JESD204B specification.

Interface Power-Up and Input Termination

Before using the JESD204B interface, it must be powered up by

setting Register 0x200, Bit 0 = 0. In addition, each physical lane

(PHY) that is not being used (SERDINx±) must be powered

down. To do so, set the corresponding Bit x for Physical Lane x

in Register 0x201 to 0 if the physical lane is being used, and to 1

if it is not being used.

The AD9175 autocalibrates the input termination to 100 Ω at

dc. This calibration routine is performed automatically when

the JESD204B interface blocks are configured and does not

require any additional SPI register writes.

Receiver Eye Mask

The AD9175 is compatible with the JESD204B specification

regarding the receiver eye mask and is capable of capturing data

that complies with the mask in Figure 56. Figure 56 shows the

receiver eye normalized to the data rate interval. The AD9175

also supports an increased insertion loss limit, as defined in the

Equalization section.

525

–55

–525

1.00

0.35

0.5

0.65

TIME (UI)

RECEIVER EYE MASK

Figure 56. Receiver Eye Mask

Clock Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

Data Rate = DAC Rate/Total Interpolation

Lane Rate = (M/L) × NP × (10/8) × Data Rate

Byte Rate = Lane Rate/10

This relationship comes from 8-bit/10-bit encoding, where each

byte is represented by 10 bits.

PCLK Rate = Byte Rate/4 = Lane Rate/40

The processing clock is used for a quad-byte decoder.

Frame Rate = Byte Rate/F

where F is defined as octets per frame per lane.

PCLK Factor = Frame Rate/PCLK Rate = 4/F

where:

M is the JESD204B parameter for converters per link, which is

the effective number of converters as seen by the JESD204B

interface (not necessarily equal to the number of DAC cores).

L is the JESD204B parameter for lanes per link.

F is the JESD204B parameter for octets per frame per lane.

NP is the JESD204B parameter for the total number of bits

per sample.

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer N techniques to

achieve clock synthesis. The entire SERDES PLL is integrated

on chip, including the VCO and the loop filter. The SERDES

PLL is capable of providing quadrature clocks to allow a wide

range of data rates (3 Gbps to 15.4 Gbps) with no gaps. These

clocks are the input to the CDR block that is described in the

Clock and Data Recovery section.

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