AD9175 datasheet(96/150 Pages) AD

96 / 150 page

AD9175

Data Sheet

Rev. A | Page 96 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

AC couple SYSREF±.

DC couple SYSREF±.

[5:1]

RESERVED

Reserved.

0x0

R/W

SYSREF_PD

Power down the SYSREF± receiver and

synchronization circuitry. If using

Subclass 0, set this bit to 1 because the

SYSREF± pins are not used.

0x0

R/W

SYSREF± receiver is powered on.

SYSREF± receiver is powered down.

0x085

NVM_CTRL1

RESERVED

Reserved.

0x0

[6:4]

NVM_CTRL1A

NVM control. Set this control to 1 at the

start of the configuration sequence (as shown

in the Start-Up Sequence section) and set

to 0 at the end of the start-up routine when

no longer programming the device.

0x1

R/W

[3:2]

RESERVED

Reserved.

0x0

NVM_CTRL1B

NVM control. Set this control to 1 at the start

of the configuration sequence (as shown in

the Start-Up Sequence section) and set to 0 at

the end of the start-up routine when no

longer programming the device.

0x1

R/W

NVM_CTRL1C

NVM control. Set this control to 0 at the

start of the configuration sequence (as

shown in the Start-Up Sequence section)

and set to 1 at the end of the start-up

routine when no longer programming the

device.

0x1

R/W

0x08D

ADC_CLK_CTRL0

[7:5]

RESERVED

Reserved.

0x0

[4:0]

CLKOUT_SWING

Controls the swing level of the ADC clock

driver. Swing can be negative (inverts clock).

0x0

R/W

The calculation for Code 0 to Code 9 is as

follows:

ADC driver swing = 993 mV − CLKOUT_

SWING × 77 mV.

The calculation for Code 10 to Code 19 is as

follows:

ADC driver swing = (20 − CLKOUT_SWING ×

77 mV) − 1 V.

0x08F

ADC_CLK_CTRL2

[7:1]

RESERVED

Reserved.

0x0

PD_CLKOUT_

DRIVER

Powers down the CLKOUT± output driver.

0x0

R/W

0x090

DAC_POWERDOWN

[7:2]

RESERVED

Reserved.

0x0

DAC_PD1

Powers down DAC1.

0x1

R/W

Power up DAC1.

Power down DAC1.

DAC_PD0

Powers down DAC0.

0x1

R/W

Power up DAC0.

Power down DAC0.

0x091

ACLK_CTRL

[7:1]

RESERVED

Reserved.

0x0

R/W

ACLK_

POWERDOWN

Analog clock receiver power-down.

0x1

R/W

0x094

PLL_CLK_DIV

[7:2]

RESERVED

Reserved.

0x0

PLL_VCO_DIV3_EN

Enable PLL output clock divide by 3.

0x0

R/W

PLL_VCO_DIV2_EN

Enable PLL output clock divide by 2.

0x0

R/W

DAC clock = PLL VCO clock frequency.

DAC clock = PLL VCO clock frequency ÷ 2.

AD9175 Datasheet(PDF) 96 Page - Analog Devices

AD9175 Datasheet(HTML) 96 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL