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AD9175 Datasheet(PDF) 9 Page - Analog Devices |
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AD9175 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 150 page  Data Sheet AD9175 Rev. A | Page 9 of 150 Parameter Symbol Test Comments/Conditions Min Typ Max Unit SCLK to SDIO Hold Time tDH 0.537 ns CS to SCLK Setup Time tS 1.036 ns SCLK to SDIO Data Valid Time tDV 9.6 ns SCLK to SDO Data Valid Time tDV 13.7 ns CS to SDIO Output Valid to High-Z Not shown in Figure 52 or Figure 53 5.4 ns CS to SDO Output Valid to High-Z Not shown in Figure 52 or Figure 53 9.59 ns INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1) Voltage Input High VIH 1.48 V Low VIL 0.425 V Current Input High IIH ±100 nA Low IIL ±100 nA OUTPUTS (SDIO, SDO) Voltage Output High VOH 0 mA load 1.69 V 4 mA load 1.52 V Low VOL 0 mA load 0.045 V 4 mA load 0.175 V Current Output High IOH 4 mA Low IOL 4 mA INTERRUPT OUTPUTS (IRQ0, IRQ1) Voltage Output High VOH 1.71 V Low VOL 0.075 V DIGITAL INPUT DATA TIMING SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LATENCY1 Channel Interpolation Factor, Main Datapath Interpolation Factor LMFC_VAR_x = 12, LMFC_DELAY_x = 12, unless otherwise noted 1×, 1×2 JESD204B Mode 153 420 DAC clock cycles JESD204B Mode 16 440 DAC clock cycles JESD204B Mode 17 590 DAC clock cycles 1×, 8×2 JESD204B Mode 3 1390 DAC clock cycles JESD204B Mode 83 1820 DAC clock cycles JESD204B Mode 9 1920 DAC clock cycles 1×, 12×2 JESD204B Mode 83 2700 DAC clock cycles JESD204B Mode 9 2840 DAC clock cycles 2×, 6×2 JESD204B Mode 3, Mode 4 1970 DAC clock cycles JESD204B Mode 5 1770 DAC clock cycles |
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