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AD9175 Datasheet(PDF) 10 Page - Analog Devices |
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AD9175 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 150 page  AD9175 Data Sheet Rev. A | Page 10 of 150 Parameter Test Conditions/Comments Min Typ Max Unit 2×, 8×2 JESD204B Mode 0 2020 DAC clock cycles JESD204B Mode 3, Mode 4 2500 DAC clock cycles 3×, 6×2 JESD204B Mode 3, Mode 4 2880 DAC clock cycles 7 JESD204B Mode 5, Mode 6 2630 DAC clock cycles 3×, 8×2 JESD204B Mode 3, Mode 4 3310 DAC clock cycles JESD204B Mode 5, Mode 6 2980 DAC clock cycles 4×, 6×2 JESD204B Mode 0, Mode 1, Mode 2 2410 DAC clock cycles 4×, 8×2 JESD204B Mode 0, Mode 1, Mode 2 3090 DAC clock cycles 6×, 6×2 JESD204B Mode 0, Mode 1, Mode 2 3190 DAC clock cycles 6×, 8×2 JESD204B Mode 0, Mode 1, Mode 2 4130 DAC clock cycles 8×, 6×2 JESD204B Mode 7 3300 DAC clock cycles 8×, 8×2 JESD204B Mode 7 4270 DAC clock cycles DETERMINISTIC LATENCY Fixed 13 PCLK4 Variable 2 PCLK cycles SYSREF± TO LMFC DELAY 0 DAC clock cycles 1 Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay. 2 The first value listed in this specification is the interpolation factor, and the second value is the main datapath interpolation factor. 3 LMFC_VAR_x = 7 and LMFC_DELAY_x = 4. 4 PCLK is the internal processing clock for the AD9175 and equals the lane rate ÷ 40. JESD204B INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 7. Parameter Symbol Test Conditions/Comments Min Typ Max Unit JESD204B SERIAL INTERFACE RATE (SERIAL LANE RATE) 3 15.4 Gbps JESD204B DATA INPUTS Input Leakage Current TA = 25°C Logic High Input level = 1.0 V ± 0.25 V 10 µA Logic Low Input level = 0 V −4 µA Unit Interval UI 333 66.7 ps Common-Mode Voltage VRCM AC-coupled −0.05 +1.1 V Differential Voltage R_VDIFF 110 1050 mV Differential Impedance ZRDIFF At dc 80 100 120 Ω SYSREF± INPUT Differential Impedance 100 Ω DIFFERENTIAL OUTPUTS (SYNCOUT0±, SYNCOUT1±)1 Driving 100 Ω differential load Output Differential Voltage VOD 320 390 460 mV Output Offset Voltage VOS 1.08 1.12 1.15 V SINGLE-ENDED OUTPUTS (SYNCOUT0±, SYNCOUT1±) Driving 100 Ω differential load Output Voltage High VOH 1.69 V Low VOL 0.045 V Current Output High IOH 0 mA Low IOL 0 mA 1 IEEE Standard 1596.3 LVDS compatible. |
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