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AD9175 Datasheet(PDF) 92 Page - Analog Devices

Part # AD9175
Description  Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
PDF  150 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9175 Datasheet(HTML) 92 Page - Analog Devices

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AD9175
Data Sheet
Rev. A | Page 92 of 150
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0
IRQ_PLL_LOCK
DAC PLL locked. If EN_PLL_LOCK is low,
IRQ_PLL_LOCK shows the current status. If
EN_PLL_LOCK is high, IRQ_PLL_LOCK
latches and pulls the IRQx pin low (x =
MUX_PLL_LOCK setting). Writing a 1 to
IRQ_PLL_LOCK when latched clears the bit.
0x0
R/W
0x028
IRQ_OUTPUT_MUX
[7:5]
RESERVED
Reserved.
0x0
R
4
MUX_SYSREF_
JITTER
If EN_SYSREF_JITTER is set, this control
chooses the IRQx output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
3
MUX_DATA_
READY
If EN_DATA_READY is set, this control
chooses the IRQx output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
2
MUX_LANE_FIFO
If EN_LANE_FIFO is set, this control chooses
the IRQx output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
1
MUX_PRBSQ
If EN_PRBSQ is set, this control chooses the
IRQx output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
0
MUX_PRBSI
If EN_PRBSI is set, this control chooses the
IRQx output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
0x029
IRQ_OUTPUT_MUX0
[7:4]
RESERVED
Reserved.
0x0
R
3
MUX_DAC0_CAL_
DONE
If EN_DAC0_CAL_DONE is set, this control
chooses the IRQx output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
[2:1]
RESERVED
Reserved.
0x0
R/W
0
MUX_PAERR0
If EN_PAERR0 is set, this control chooses the
IRQx output pin on which the event is
triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
0x02A
IRQ_OUTPUT_MUX1
[7:4]
RESERVED
Reserved.
0x0
R
3
MUX_DAC1_CAL_
DONE
If EN_DAC1_CAL_DONE is set, this control
chooses the IRQx output pin on which the
event is triggered.
0x0
R/W
0
Route IRQ trigger signal to the IRQ0 pin.
1
Route IRQ trigger signal to the IRQ1 pin.
[2:1]
RESERVED
Reserved.
0x0
R/W
0
MUX_PAERR1
If EN_PAERR1 is set, this control chooses the
IRQx output pin on which the event is
triggered.
0x0
R/W



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