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AD9175 Datasheet(PDF) 8 Page - Analog Devices |
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AD9175 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 150 page  AD9175 Data Sheet Rev. A | Page 8 of 150 Parameter Test Conditions/Comments Min Typ Max Unit Total Power Dissipation 1.2 2.05 W DUAL-LINK, MODE 3 (NCO ONLY, SINGLE-CHANNEL MODE, NO SERDES) 6 GSPS DAC rate, 300 MHz PLL reference clock, 8× total interpolation (1×, 8×), no input tone (dc internal level = 0x50FF), channel NCO = 40 MHz, main NCO = 1.8425 GHz Mode 3 AVDD1.0 All supply levels set to nominal values 410 660 mA All supplies at 5% tolerance 435 750 mA AVDD1.8 110 130 mA DVDD1.0 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values 500 780 mA All supplies at 5% tolerance 515 950 mA DVDD1.8 0.3 1 mA SVDD1.0 All supply levels set to nominal values 5 100 mA All supplies at 5% tolerance 3 120 mA Total Power Dissipation 1.11 1.671 W DUAL-LINK, MODE 4 (NCO ONLY, DUAL-CHANNEL MODE, NO SERDES) 12 GSPS DAC rate, 500 MHz PLL reference clock, 32× total interpolation (4×, 8×), no input tone (dc internal level = 0x2AFF), channel NCOs = ±150 MHz, main NCO = 2 GHz Mode 4 AVDD1.0 All supply levels set to nominal values 750 1030 mA All supplies at 5% tolerance 790 1130 mA AVDD1.8 110 130 mA DVDD1.0 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values 1200 1590 mA All supplies at 5% tolerance 1300 1750 mA DVDD1.8 0.3 1 mA SVDD1.0 5 100 mA Total Power Dissipation 2.15 2.851 W SERIAL PORT AND CMOS PIN SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 5. Parameter Symbol Test Comments/Conditions Min Typ Max Unit WRITE OPERATION See Figure 53 Maximum SCLK Clock Rate fSCLK, 1/tSCLK 80 MHz SCLK Clock High tPWH SCLK = 20 MHz 5.03 ns SCLK Clock Low tPWL SCLK = 20 MHz 1.6 ns SDIO to SCLK Setup Time tDS 1.154 ns SCLK to SDIO Hold Time tDH 0.577 ns CS to SCLK Setup Time tS 1.036 ns SCLK to CS Hold Time tH −5.3 ps READ OPERATION See Figure 52 SCLK Clock Rate fSCLK, 1/tSCLK 48.58 MHz SCLK Clock High tPWH 5.03 ns SCLK Clock Low tPWL 1.6 ns SDIO to SCLK Setup Time tDS 1.158 ns |
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