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Data Sheet

AD9175

Rev. A | Page 41 of 150

Sync Procedure

The procedure for enabling the sync is as follows:

1. Set up the DAC and the SERDES PLL, and enable the CDR

(see the Start-Up Sequence section).

2. Set Register 0x03B to 0xF1 to enable the synchronization

circuitry. If using the soft on/off feature, set Register 0x03B

to 0xF3 to ramp the datapath data before and after the

synchronization.

3. If Subclass 1, configure the SYSREF± settings as follows:

a. Set Register 0x039 (SYSREF± jitter window). See Table 24

for settings.

b. Set Register 0x036 = SYSREF_COUNT. Leave the

setting as 0 to bypass.

4. Perform a one-shot sync.

a. Set Register 0x03A = 0x00. Clear one-shot mode if

already enabled.

b. Set Register 0x03A = 0x02. Enable one-shot sync

mode.

5. If Subclass 1, send a SYSREF± edge. If pulse counting,

multiple SYSREF± edges are required. Sending SYSREF±

edges triggers the synchronization.

6. Read back the SYNC_ROTATION_DONE bit

(Register 0x03A, Bit 4) to confirm the rotation occurred.

Resynchronizing LMFC Signals

If desired, the sync procedure can be repeated to realign the

LMFC clock to the reference signal by repeating Step 2 to

Step 6, described in the Sync Procedure section. When the

one-shot sync is armed (writing Register 0x03A = 0x02), the

SYNCOUTx± signals deassert to drop the JESD204B links and

reassert after the rotation completes.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout. Data traversing from one clock domain to a

different clock domain can lead to ambiguous delays in the

JESD204B link. These ambiguities lead to nonrepeatable

latencies across the link from power cycle to power cycle with

each new link establishment. Section 6 of the JESD204B

specification addresses the issue of deterministic latency with

mechanisms defined as Subclass 1 and Subclass 2.

The AD9175 supports JESD204B Subclass 0 and Subclass 1

operation, but not Subclass 2. Write the subclass to

Subclass 0

Subclass 0 mode provides deterministic latency to within

several PCLK cycles. It does not require any signal on the

SYSREF± pins, which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same LMFC

cycle and the dual DACs must be synchronized to each other.

Subclass 1

Subclass 1 mode gives deterministic latency and allows the link

to be synchronized to within a few DAC clock cycles. Across the

full operating range, for both supply and temperature, it is

within ±2.5 DAC clock periods for a 6 GHz DAC clock rate or

±4 DAC clock periods for a 12.6 GHz DAC clock rate. If both

supply and temperature stability are maintained, the link can be

synchronized to within ±1.5 DAC clock periods for a 6 GHz

DAC clock rate or ±2.5 DAC clock periods for a 12.6 GHz DAC

clock rate. Achieving this latency requires an external, low jitter

SYSREF± signal that is accurately phase aligned to the DAC clock.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system, as follows:

•

The SYSREF± signal distribution skew within the system

must be less than the desired uncertainty.

•

The total latency variation across all lanes, links, and

devices must be ≤12 PCLK periods, which includes both

variable delays and the variation in fixed delays from lane

to lane, link to link, and device to device in the system.

ILAS

FIXED DELAY

VARIABLE

DELAY

POWER CYCLE

VARIANCE

DATA

LMFC

ALIGNED DATA

AT Rx OUTPUT

DATA AT

Tx INPUT

DATA

CHANNEL

LOGIC DEVICE

(JESD204B Tx)

JESD204B Rx

LINK DELAY = DELAYFIXED + DELAYVARIABLE

Figure 65. JESD204B Link Delay = Fixed Delay + Variable Delay

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