AD9175 datasheet(98/150 Pages) AD

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AD9175

Data Sheet

Rev. A | Page 98 of 150

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x100

DIG_RESET

[7:1]

RESERVED

Reserved.

0x0

DIG_DATAPATH_PD

Holds all digital logic (SERDES digital, digital

clock generation, and digital datapath) in

reset until clock tree is stable.

0x1

R/W

Normal operating mode.

Holds the digital logic in reset. Must be

released (set to 0) after clocks to the chip

are stable (PLL and DLL blocks are locked)

to use the digital datapath.

0x110

JESD_MODE

MODE_NOT_IN_

TABLE

Programmed JESD204B mode and

interpolation mode combination is not

valid. Select a different combination.

0x0

COM_SYNC

Combine the SYNCOUTx± signals in dual

link case.

0x0

R/W

[5:0]

JESD_MODE

Sets the JESD204B mode configuration. See

Table 13 for the JESD204B supported

operating modes and compatible

interpolation rates. Bit 5 of this control

determines single link (set to 0) or dual link

(set to 1). Bits[4:0] set the desired JESD204B

mode according to Table 13.

0x20

R/W

0x111

INTRP_MODE

[7:4]

DP_INTERP_MODE

Sets main datapath interpolation rate. See

Table 13 for the JESD204B supported

operating modes and compatible JESD204B

modes and channel interpolation rates.

0x8

R/W

0x1

1×.

0x2

2×.

0x4

4×.

0x6

6×.

0x8

8×.

0xC

12×.

[3:0]

CH_INTERP_MODE

Sets channel interpolation rate. See Table 13

for the JESD204B supported operating

modes and compatible JESD204B modes

and main datapath interpolation rates.

0x4

R/W

0x1

1×.

0x2

2×.

0x3

3×.

0x4

4×.

0x6

6×.

0x8

8×.

0x112

DDSM_DATAPATH_

CFG

RESERVED

Reserved.

0x0

EN_CMPLX_MOD

Modulator switch mode selection. This

control allows modifying Configuration 3 of

the modulator switch to allow complex

(I/Q) data from each NCO to pass to DACx.

This function depends on the settings

applied to Bits[5:4] in this register,

Bits[5:4] of this register are set to 0b11

(Modulator Switch Configuration 3). This

control is paged by the MAINDAC_

PAGE bits in Register 0x008.

Switch configuration is as defined by

Bits[5:4].

AD9175 Datasheet(PDF) 98 Page - Analog Devices

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