ADPD144RI datasheet(30/34 Pages) AD

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ADPD144RI

Data Sheet

Rev. A | Page 30 of 34

Address

Data

Bit

Default

Access

Name

Description

0x01

[15:9]

0x00

R/W

Reserved

0x00

R/W

FIFO_INT_MASK

Sends an interrupt when the FIFO data length has exceeded the FIFO

length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt.

0x1

R/W

Reserved

0x1

R/W

SLOTB_INT_MASK

Sends an interrupt on the Time Slot B sample. A 0 enables the interrupt.

0x1

R/W

SLOTA_INT_MASK

Sends an interrupt on the Time Slot A sample. A 0 enables the interrupt.

[4:0]

0x1F

R/W

Reserved

0x02

[15:3]

0x0000

R/W

Reserved

0x0

R/W

INT_ENA

INT enable.

0: disable the INT pin. The INT pin floats regardless of interrupt status.

The status register (Address 0x00) remains active.

1: enable the INT pin.

0x0

R/W

INT_DRV

INT drive.

0: the INT pin is always driven.

1: the INT pin is driven when the interrupt is asserted. Otherwise, it is

left floating and requires a pull-up or pull-down resistor, depending on

polarity (operates as open-drain). Use this setting if multiple devices

need to share the INT pin.

0x0

R/W

INT_POL

INT polarity.

0: the INT pin is active high.

1: the INT pin is active low.

0x06

[15:14]

0x0

R/W

Reserved

[13:8]

0x00

R/W

FIFO_THRESH

FIFO length threshold. An interrupt is generated when the number of

data words in the FIFO exceeds the value in FIFO_THRESH. The

interrupt pin automatically deasserts when the number of data words

available in the FIFO no longer exceeds the value in FIFO_THRESH.

[7:0]

0x00

R/W

Reserved

0x08

[15:0]

0x0416

DEV_ID

Device ID.

0x0A

[15:12]

0x0

Reserved

[11:0]

0x000

CLK_RATIO

When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device

calculates the number of 32 MHz clock cycles in two cycles of the

32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the

CLK_RATIO bits.

0x10

[15:2]

0x000

R/W

Reserved

[1:0]

0x0

R/W

Mode

Determines the operating mode of the ADPD144RI.

0x0: standby.

0x1: program.

0x2: sample.

0x11

[15:14]

0x1

R/W

Reserved

0x0

R/W

RDOUT_MODE

Readback data mode for extended data registers.

0x0: block sum of N samples.

0x1: block average of N samples.

0x1

R/W

FIFO_OVRN_PREVENT

0x0: wrap around FIFO, overwriting old data with new.

0x1: new data if FIFO is not full (recommended setting).

[11:9]

0x0

R/W

Reserved

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